KISHINE Keiji

写真a

Title

Professor

Research Fields, Keywords

LSI design

Mail Address

E-mail address

Degree 【 display / non-display

  • Doctor(Informatics)  Kyoto University  2006.03

Campus Career 【 display / non-display

  • University of Shiga Prefecture  School of Engineering  Department of Electronic Systems Engineering  Professor   2016.04 - Now

  • University of Shiga Prefecture  School of Engineering  Department of Electronic Systems Engineering  Associate Professor   2008.04 - 2016.03

External Career 【 display / non-display

  • NIPPON TELEGRAPH AND TELEPHONE  Chief Researcher   2004.10 - 2007.03

  • NIPPON TELEGRAM NAD TELEPHONE     2007.04 - 2008.03

Academic Society Affiliations 【 display / non-display

  • IEEE

 

Research theme 【 display / non-display

  • A ultra-high speed integrated circuit design

    integrated circuit low power ultra-high speed communication system

Papers 【 display / non-display

  • Simple and Low Power Highly Sensitive Frequency Demodulator Circuit for 10-Gb/s Transmission System  for Labeling Signal

    Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, and Keiji Kishine

    IEIE  IEIE JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE(IEIE JSTS)  17 (6)   733 - 740  2017.12

    Joint Work  Joint(The main charge)

  • Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS

    Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine

    IEIE  IEIE JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE(IEIE JSTS)  17 (6)   742 - 749  2017.12

    Joint Work  Joint(The main charge)

  • Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS

    Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, and Makoto Nakamura

      International SoC Design Conference (ISOCC2017)    2017.11

    Joint Work  

  • FPGA-Based Transceiver Circuit for Labeling Signal Transmission System

    Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

      International SoC Design Conference (ISOCC2017)    2017.11

    Joint Work  

  • Compact Implementation IIR filter in FPGA for Noise Reduction of Sensor Signal

    Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

      International SoC Design Conference (ISOCC2017)    2017.11

    Joint Work  

  • 25-Gb/s Clock and Data Recovery IC Using Latch Load Combined with CML Buffer Circuit for Delay  Generation with 65-nm CMOS

    Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi,  Daichi Omoto, Hiromi Inaba, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka and Keiji Kishine

    IEEE CAS   IEEE International Symposium on Circuits and Systems  (ISCAS2017)    2017.05

    Joint Work  

  • Cross Current Suppression Control for Parallel Operation System Contructed with Two Electric Power  Converters under Different Output

    Ryota Fujisawa, Hiromi Inaba, Keiji Kishine, Keisuke Ishikura, and Kazuki Ikebata

    ICEMS 2016  The 19th International Conference on Electrical Machines and Systems (ICEMS2016)    2016.11

    Joint Work  

  • 36-Gb/s CDR IC using simple passive loop filter combined with a passive load in phase detector

    Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine

      International SoC Design Conference (ISOCC2016)    2016.10

    Joint Work  

  • Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system

    Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, and Keiji Kishine

      International SoC Design Conference (ISOCC2016)    2016.10

    Joint Work  Joint(The main charge)

  • Design of High-Linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS

    Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine

      International SoC Design Conference (ISOCC2016)    2016.10

    Joint Work  

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