Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/elex.20.20230238

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ICECS58634.2023.10382799

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ISOCC59558.2023.10396067

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings   Participation form：Joint(The vice charge)  

A burst-mode transimpedance amplifier (TIA) receives burst signals, which are intermittent signals. To reduce the power consumption during the idle times, we propose a burst-mode TIA with automatic power saving in 65-nm CMOS. It enables to provide a stable operation without a DC wander effect while receiving the burst signal. The post-layout simulation results show that the designed TIA can automatically reduce the power consumption during the idle times by 54.2% compared to that during the active times.

DOI： 10.1109/ICECS202256217.2022.9970848

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings  

Recently, radio-wave sensors have been utilized in automotive radar and biological sensing applications. Although beamforming using an array antenna is effective method for changing the radiation directivity, the phase-shift error causes degradation of the directivity significantly. In this paper, we propose a fine-tuning phase shifter with a vector synthesizer, which enables to control the phase-shift amount continuously in 24-GHz band. From the measurement results of the fabricated phase shifter using 65-nm CMOS technology, the variable phase-shift amount over a range of 360◦ is obtained continuously. In addition, the estimated radiation patterns show that the phase-shift and amplitude errors of the fabricated phase shifter are acceptable.

DOI： 10.1109/ICECS202256217.2022.9970921

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Proceedings - International SoC Design Conference 2022, ISOCC 2022   Participation form：Joint(The vice charge)  

We propose a method for implementing an LSTM-based multiple-people identification system on a small-scale FPGA. To reduce the hardware-resource usage, we introduce a digit adjustment and bit reduction method for converting the floating-point type to the fixed-point type with high precision. It enables not only to reduce the hardware-resource usage without degrading the identification accuracy but also to shorten the computation time by 50% compared to that of the conventional floating-point type.

DOI： 10.1109/ISOCC56007.2022.10031374

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Proceedings - International SoC Design Conference 2022, ISOCC 2022   Participation form：Joint(The vice charge)  

This paper describes a proposal for a classification interface for computational resources distribution in CPS. The classification interface enables to distribute processing to the different computational resources (CPU and FPGA) automatically depending on the type of the processing. As a result, the total processing time is shortened by 50.9% compared to that of the system without the classification interface.

DOI： 10.1109/ISOCC56007.2022.10031427

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Proceedings - International SoC Design Conference 2022, ISOCC 2022   Participation form：Joint(The vice charge)  

In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAMbased system.

DOI： 10.1109/ISOCC56007.2022.10031293

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The vice charge)  

DOI： 10.1109/MWSCAS54063.2022.9859338

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The main charge)  

DOI： 10.1109/MWSCAS54063.2022.9859435

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Electronics (Switzerland)  

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dBΩ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 µm × 225 µm.

DOI： 10.3390/electronics11060854

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEIE   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEIE   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEIE   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEIE   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ACM   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The vice charge)  

DOI： 10.1109/ICECS53924.2021.9665522

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEIE   Participation form：Joint(The vice charge)  

DOI： 10.5573/JSTS.2021.21.1.029

Language：English   Publishing type：Research paper (scientific journal)   Publisher：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021  

This paper proposes a 5-Gb/s four-level pulse amplitude modulation (PAM4) transmitter using compensation circuit in data transmission systems. In PAM4 systems, the signal amplitude requires smaller rising and falling times. To achieve this, we adopted an analog feed forward equalizing (FFE) for the compensation in PAM4 transmitter. To confirm the advantage of the proposed technique, we fabricated a 5-Gb/s PAM4 transmitter IC in an 180-nm CMOS process for this work. The measured rising and falling times were 18% and 13% smaller than those without FFE, respectively.

DOI： 10.1109/ICEIC51217.2021.9369819

Scopus

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021  

Regression and classification are necessary for biometric systems and carried out using machine learning. A method for regression and classification is long short-term memory (LSTM). We proposed and implemented algorithms for low-energy LSTM for the regression of microwave-sensor signals into a small-scale FPGA. We found that our FPGA-based parallel (including unrolled)-pipelined algorithm decreased the computation time by 95% compared with the FPGA-based sequential algorithm. In addition, the amount of energy consumption with the proposed algorithm was reduced by 92% and 91% compared with that with a high-end GPU and CPU, respectively.

DOI： 10.1109/ICEIC51217.2021.9369806

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ACM   Participation form：Joint(The vice charge)  

DOI： 10.1145/3394885.3431646

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEIE Transactions on Smart Processing and Computing  

Biometric systems require the regression and classification of biological sensing data, which are both carried out using machine learning. Long short-term memory (LSTM) is one of the most common methods used for regression and classification. We have developed and implemented a low-energy LSTM algorithm for the regression of microwave sensor signals in a small-scale FPGA. Experimental results show that the FPGA-based parallel-pipelined unrolled algorithm can reduce the computation time by 95% compared to an FPGA-based sequential algorithm. In addition, we found that the power consumption can be reduced by 92% and 91% compared to that obtained with a high-end GPU and CPU, respectively.

DOI： 10.5573/IEIESPC.2021.10.5.416

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Journal of Semiconductor Technology and Science   Participation form：Joint(The vice charge)  

© 2020, Institute of Electronics Engineers of Korea. All rights reserved. We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, band-width, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-mm CMOS type.

DOI： 10.5573/JSTS.2020.20.2.177

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE   Participation form：Joint(The main charge)  

DOI： 10.1587/transele.2018CTP0007

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Journal of Semiconductor Technology and Science  

© 2019, Institute of Electronics Engineers of Korea. All rights reserved. We implemented and evaluated our newly developed binary labeling signal transmission system using field-programmable gate arrays. In this system, the state of “0” or “1” of labeling signals is related to modulation or non-modulation of frame signals, and the labeling signals can be multiplexed to frame signals and transmitted without changing the configuration of the original frame signal. We designed a modulation-system protocol for implementing the above system and propose a digital smoothing technique for stabilizing a phase-locked loop circuit. We verified that our digital smoothing technique prevents bit error of the modulated frame signals in the implemented transmitter. The labeling signal multiplexed to the frame signals is demodulated without bit error in the implemented transceiver.

DOI： 10.5573/JSTS.2019.19.3.276

Scopus

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE SSCS   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE CAS   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English  

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ASSCC.2015.7387470

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5V to 1.2V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65 nm CMOS process. Area of the AES core is 0 : 22 mm(2) and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5V to 1.2V which enables the reduction of power dissipation, for example, of 17% at 400MHz operation.

DOI： 10.1587/transele.E98.C.504

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

A multi-rate burst-mode clock and data recovery ( BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW.

DOI： 10.1109/TCSI.2015.2416812

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：NATURE PUBLISHING GROUP  

The brain is composed of many different types of neurons. Therefore, analysis of brain activity with single-cell resolution could provide fundamental insights into brain mechanisms. However, the electrical signal of an individual neuron is very small, and precise isolation of single neuronal activity from moving subjects is still challenging. To measure single-unit signals in actively behaving states, establishment of technologies that enable fine control of electrode positioning and strict spike sorting is essential. To further apply such a single-cell recording approach to small brain areas in naturally behaving animals in large spaces or during social interaction, we developed a compact wireless recording system with a motorized microdrive. Wireless control of electrode placement facilitates the exploration of single neuronal activity without affecting animal behaviors. Because the system is equipped with a newly developed data-encoding program, the recorded data are readily compressed almost to theoretical limits and securely transmitted to a host computer. Brain activity can thereby be stably monitored in real time and further analyzed using online or offline spike sorting. Our wireless recording approach using a precision motorized microdrive will become a powerful tool for studying brain mechanisms underlying natural or social behaviors.

DOI： 10.1038/srep07853

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Energy-efficiency has become the driving force of today's LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.

DOI： 10.1109/ISQED.2015.7085421

Web of Science

Language：Japanese  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper proposes a radiation-hardened phase-locked loop (RH-PLL) with a switchable dual modular redundancy (DMR) structure. After radiation strikes, unhardened PLLs suffer clock perturbations. Conventional RH-PLLs have been proposed to reduce recovery time after perturbation. However, this recovery still requires tens of clock cycles. Our proposal involves 'detecting' and 'switching', rather than 'recovering' from clock perturbation. Detection speed is crucial for robust perturbation-immunity. We identify types of clock perturbation and then propose a set of detectors to detect each type. With this method, the detectors guarantee high-speed detection that leads to perturbation-immune switching from a radiated clock to an undistorted clock. The proposed RH-PLL was fabricated and then verified with a radiation test on real silicon.

DOI： 10.1587/transele.E97.C.325

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and Power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6 V to 1.2 V. We fabricated the BBG in a 65 nm CMOS process to control 0.1 mm(2) of core circuit with the area overhead of 1.4% for the BBG.

DOI： 10.1587/transfun.E97.A.734

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper presents an analysis of radiation-induced clock-perturbation in phase-locked loop (PLL). Due to a trade-off between cost, performance, and reliability, radiation hardened PLL design need robust strategy. Thus, evaluation of radiation vulnerability is important to choose the robust strategy. The conventional evaluation-method is however based on brute-force analysis - SPICE simulation and experiment. The presented analysis result eliminates the brute-force analysis in evaluation of the radiation vulnerability. A set of equations enables to predict the radiation-induced clock-perturbation at the every sub-circuits. From a demonstration, the most vulnerable nodes have been found, which are validated using a PLL fabricated with 0.18 mu m CMOS process.

DOI： 10.1587/transfun.E97.A.768

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A 25-Gb/s inductorless output buffer circuit with a pre-emphasis is proposed. We designed the circuit parameters according to the frequency characteristics of the emphasized signal. To confirm the advantages of the emphasis circuit, we fabricated an output buffer IC in a 65-nm CMOS process. The proposed circuit has a control voltage to adjust the emphasis amplitude according to the load outside the chip. Measurement results showed that the jitters were 40% lower with the emphasis circuit than without, indicating that our proposed configuration can be applied to the design of output buffer circuits for higher operation speed.

DOI： 10.1109/ISOCC.2014.7087578

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. While FGBB is effective in reducing variability and power consumption, a number of BBGs are required on a die and therefore simplified design of BBGs is necessary. This paper proposes a cell-based design of a BBG that generates forward and reverse body bias voltages only from a core supply voltage ranging from the near threshold of 500mV to the nominal voltage of 1.2V. This wide operating range is achieved by a low voltage error amplifier with a V-th biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm low power CMOS process to control 0.22mm(2) of core circuit with the area overhead of 2.3% for the BBG.

DOI： 10.1109/ASSCC.2014.7008858

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A 12.5-Gb/s burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops which operate complementarily. The same type of circuit configurations are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a 12.5-Gb/s-BCDR IC with the 65-nm-MOSFET process. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gis. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW, respectively.

DOI： 10.1109/ISCAS.2014.6865731

Web of Science

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper presents high-speed and area-efficient laser-diode driver with interwoven inductor in a 0.18-mu m CMOS. We interweave ten peaking inductors for area-effective implementation as well as performance enhancement. Interwoven inductor can not only achieve area-efficiency but also tune frequency characteristic. Mutual inductances of interwoven inductor enhance bandwidth and suppress group delay dispersion. The test chip area is 0.32 mm(2) and the maximum operating speed is 25 Gb/s.

DOI： 10.1109/ASPDAC.2013.6509578

Web of Science

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1155/2013/272070

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper presents a slow-wave transmission line with thin pillars on strips shield. Slow-wave transmission lines are mostly used as stub filters. The proposed structure with pillars has higher capacitance and inductance per unit length of the line. Thus, high phase constant and quality factor can be achieved. We compare simulation results between the proposed structure and conventional lines for millimeter-wave CMOS. The proposed line gives higher phase constant of 3.1 rad/mm and high quality factor of 21.6 at 60 GHz. © 2013 IEEE.

DOI： 10.1109/SaPIW.2013.6558341

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper discusses loss of on-chip transmission-line in terahertz region. Above 100 GHz, modeling of on-chip transmission-line is an important issue. We evaluate the impact of eddy current and anomalous skin effect by a field solver. Simulation results show that eddy current in dummy fills has higher impact of 10% on transmission-line loss. Anomalous skin effect is not negligible, but its impact is about 5% at 100 GHz. © 2013 IEEE.

DOI： 10.1109/IMFEDK.2013.6602261

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper proposes a perturbation-immune radiation-hardened PLL with a switchable dual modular redundancy (DMR) structure. By a radiation-strike, a PLL has clock-perturbation for a while. Conventional RHPLLs are proposed to reduce recovery-time which is the time to recover from perturbation. However, recovery still needs tens of clock cycles. Our proposal is 'detecting' and 'switching' instead of 'recovering' clock-perturbation. For robust perturbation-immunity, detecting speed is important. We identify types of clock-perturbation and-then propose a set of detectors to detect each type. With this, detectors guarantee high speed in detection. © 2013 IEEE.

DOI： 10.1109/IOLTS.2013.6604063

Scopus

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation.

DOI： 10.1109/TSM.2012.2198677

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 mu m CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

DOI： 10.1587/transfun.E95.A.479

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ASPDAC.2012.6165018

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper discusses radiation loss of on-chip transmission-line. Since terahertz applications of integrated circuits are emerging, precise modeling in terahertz region is needed. We evaluate conductor loss, dielectric loss and radiation loss of on-chip transmission-line by a full-wave field solver. Simulation results show that design focusing conductor loss may cause large radiation loss in terahertz region. Quantitative evaluation of the impact of radiation loss is demonstrated. Also we show that thick signal wire and differential line is effective to reduce the loss. © 2012 IEEE.

DOI： 10.1109/SaPIW.2012.6222926

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

To compensate the die-to-die and location correlated variation, we propose to split digital circuit to sub-mm-scale area controlling each area with an on-chip forward/reverse body bias generator (BBG). The proposed BBG is configured as a feedforward control system to achieve small area. The BBG is realized by combining a low output resistance DAC and a charge pump type level shifter. The BBG design is implemented with 1.2V thin gate oxide MOSFET in a 65nm CMOS technology. The simulation and measurement results show that the variation is compensated with an area overhead as small as 2%. © 2011 IEEE.

DOI： 10.1109/ASSCC.2011.6123641

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper discusses a method to evaluate anomalous skin effect. Anomalous skin effect (ASE) is a phenomenon which appears when the skin depth becomes comparable to the mean free path of electrons. In anomalous region, the effective resistivity depends on skin depth. Thus it is difficult to evaluate by field-solvers. The proposed method realizes field simulation considering ASE by gradient resistivity. Simulation result shows that the resistance increase more rapid than classical skin effect above 100GHz. The effect on the resistance is 5% at 100GHz and 10% at 300GHz.

DOI： 10.1109/SPI.2011.5898859

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ICMTS.2011.5976878

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

J-GLOBAL

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

A laser-diode (LD) driver with interwoven mutually-coupled peaking inductors for high-speed optical networks is presented. Six and four inductors are interwoven into two sets of inductors for area-effective implementation as well as performance enhancement. The proposed circuit is fabricated in CMOS 0.18-mu m process. The circuit area is 0.34mm(2) and the maximum operating speed is 16Gbps. Compared to a conventional LD driver in 0.18-mu m CMOS, the proposed circuit achieves 1.6 times faster operation, 26% smaller area with 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current.

DOI： 10.1109/CICC.2010.5617416

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

A design procedure for generating predictive MOS-FET models is proposed. Due to evolving nature of future prediction, predictive models based on a certain prediction soon become absolute. We have therefore developed a design procedure for maintaining compatibility with most up-to-date prediction such as ITRS. The design procedure can generate predictive RF models for the first time. Details of the design procedure for BSIM4 as a core model are explained, with an application to LNA design example. © 2010 IEEE.

DOI： 10.1109/SOCC.2010.5784704

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/CICC.2010.5617416

Language：English   Publishing type：Research paper (scientific journal)  

As the minimum feature size shrinks down far below sub-wavelength, Design for Manufacturability or layout regularity plays an important role for maintaining pattern fidelity in photolithography. However, it also incurs overheads in circuit performances due to parasitic capacitance. In this paper, we examine the effect of layout regularity on printability and circuit performance by lithography simulation and transistor-level simulation. It is shown that regularity-enhanced cells provide better Critical Dimension (CD) stability under defocus and lead to delay increase. Then we evaluate the effect of layout regularity by a real chip measurement in 90 nm, 65 nm and 45 nm processes. For example, in a 65 nm process, inverter Ring Oscillators (ROs) that have the smallest poly pitch with dummy-poly insertion exhibits 19% reduction of WID and D2D variation with delay overhead of 2.5%, compared to the ROs without dummy-poly insertion. However, we have observed that the effect of layout regularity varies depending on fabrication processes and circuit structures. It is therefore important to obtain the best trade-off among performance overhead and variability reduction for each process technology. © 2010 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.3.130

Scopus

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper reports measurement results of on-chip transmission-line with split-ring resonators. Split-ring resonator (SRR) has attracted attention as an implementation of metamaterial (left-handed material). However when simple SRR is implemented in LSIs, the resonance frequency becomes around 200GHz and it is too high to employ on on-chip circuits. We designed a stacked SRR to lower the resonant frequency in a 0.18//m CMOS. Measurement results show that the stacked SRRs can realize the resonance frequency below 50GHz. Also measurement results show a guideline of area effective implementation of on-chip SRR. © 2010 IEEE.

DOI： 10.1109/SPI.2010.5483544

Scopus

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the Output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80% error in worst case. The error of the proposed method is less than 20%.

DOI： 10.1587/transfun.E92.A.3070

Web of Science

Language：Japanese  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-off among manufacturability, cost, and performance for each process technology. This paper discusses the efiect of layout regularity on printability and circuit performance in 90 45nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows in a 45nm process. We demonstrate the quantitative evaluation of the trade-off between printability and circuit performance of regularity-enhanced standard cells.

DOI： 10.1109/ISQED.2009.4810293

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a method to realize on-chip metamaterial transmission-line. Since the resonant frequency of split-ring resonator (SRR) depends on the size strongly, it is difficult to realize metamaterial transmission-line in integrated circuits. If we implement a conventional SRR to on-chip transmission-line, the resonant frequency is around 200GHz. We propose a stacked SRR using on-chip multi-layer interconnect. The stacked SRR is evaluated by a field-solver and the experimental results verify that the stacked SRR can realize the resonant frequency below 60GHz.

DOI： 10.1109/APMC.2009.5384480

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ASPDAC.2009.4796511

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/SPI.2009.5089867

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.

DOI： 10.1093/ietfec/e91-a.12.3474

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

This paper discusses the effect of dummy fills on the performance of spiral inductors. In Si-CMOS processes that use copper wire, metal dummy fills are required to prevent thickness fluctuation in the chemical mechanical polishing stage. Dummy fills have been thought to affect the wire capacitance; however, in high frequency, dummy fills also affect the wire resistance and the wire inductance due to the eddy current in dummy fills. This work evaluates the effect of the dummy fills by three-dimensional field solver and proposes a structure to suppress the effect of dummy fills. Experimental results show that the proposed method can decrease the effect of dummy fills on the Q-factor by 83% compared with the conventional dummy fill insertion.

DOI： 10.1109/TMTT.2008.2007362

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)  

In this paper, we propose an approximation method for the statistical MAX operation such that it results in a normal distribution good for the worst-case delay analysis. The important operation in SSTA is SUM and MAX of distributions. In general, the delay variation is modeled as normal distribution. The result of SUM operation of two normal distributions is also normal distribution. On the other hand, the result of MAX operation is not normal distribution. Thus approximation to normal distribution is commonly used. We also explain that the proposed MAX operation at each gate also contributes to the accurate estimation in the worst-case delay analysis of the whole circuit. Experimental results show that the proposed method leads to a good approximation for a normal distribution resulted from MAX operation of normal distributions with and without correlation, and the approximation improves the accuracy of the worst-case delay analysis. In a circuit example, the errors of worst-case delay computed by the previous method are about 20%, and the errors computed by the proposed method are under 5%. © 2008 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.1.116

Scopus

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

J-GLOBAL

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

J-GLOBAL

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/MWSYM.2008.4632950

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ASPDAC.2008.4483959

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ICCD.2008.4751859

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

J-GLOBAL

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

J-GLOBAL

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip trans mission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

DOI： 10.1093/ietele/e90-c.6.1274

Web of Science

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified. We also apply the proposed model to design trade-off analysis.

DOI： 10.1109/CICC.2007.4405866

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/ASPDAC.2007.357970

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1145/1231996.1232006

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

DOI： 10.1109/SPI.2006.289229

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper reports measurement results of on-chip interconnects with CMP dummy fill. CMP dummy fill is a floating metal for metal density adjustment. In high frequency above 10GHz, the eddy current induced in dummy fills affects the interconnect loss. We fabricated test structures of on-chip interconnect with dummy fills. From the measurement results, the effect of the dummy fills on the wire resistance is not negligible even if the ground wires are adjacent to the signal wire. The dummy fills in the upper/lower metal layer affect the wire resistance and the resistance increases by 20% at 50GHz.

DOI： 10.1109/SPI.2007.4512261

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

This paper discusses the effect of dummy fills on on-chip interconnect characteristics. The effect of dummy fills has been discussed from the viewpoint of the capacitance. However in high frequency, the magnetic coupling between the signal current and the eddy current in the dummy fills is not negligible. We evaluate the characteristics of on-chip interconnects with dummy fills by a 3D field solver. The size and the location of dummy fills are varied. We also evaluate the effect of dummy fills in the other interconnect layers. Experimental results shows that the impact of the dummy fills on the resistance and the attenuation is not negligible in high frequency such as 50GHz, and the dummy fills in the other layers have strong effect to the interconnect characteristics. The increase of the attenuation constant due to the dummy fills becomes 20% in maximum. ©2006 IEEE.

DOI： 10.1109/SPI.2006.289243

Scopus

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. Experimental results show that the proposed method provides accurate transition waveforms over various interconnect topologies.

DOI： 10.1093/ietfec/e89-a.12.3585

Web of Science

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow. key words: substrate, interconnect, resistance, inductance, SoC

DOI： 10.1093/ietfec/e89-a.12.3560

Web of Science

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

J-GLOBAL

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The vice charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.

DOI： 10.1093/ietele/e89-c.3.327

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/EPEP.2006.321214

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. We experimentally verify that the proposed method provides accurate transition waveforms over various interconnect topologies.

Web of Science

Language：English   Publishing type：Doctoral thesis  

Language：English   Publishing type：Doctoral thesis  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (international conference proceedings)  

DOI： 10.1109/CICC.2005.1568742

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper discusses shielding effect of power/ground wires in lower layer. A conducting substrate affects characteristics of on-chip transmission line. However in many cases on actual chips, there are P/G wires between the signal wire and the substrate that may shield the substrate coupling. We show measurement and simulation results of on-chip transmission-lines with narrow yet many power/ground wires in a lower layer. Experimental results show that narrow power/ground wires in a lower layer in parallel to the signal wire, which are common in LSI power distribution network, shield substrate coupling and suppress substrate loss. On the other hand, orthogonal power/ground wires in a lower layer hardly mitigate substrate coupling.

DOI： 10.1109/SPI.2005.1500944

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper propose a systematic method to select power/ground wires that should be considered in interconnect R-L extraction. The return current distribution affects loop characteristic of interconnects. To extract exact RL value, all of return paths have to be considered. However it is impossible because there are huge number of P/G wires in LSIs. As more wires are considered, the extraction accuracy improves but the extraction cost increases undesirably. The proposed method focuses the energy dissipated at P/G wires and utilizes it for screening return paths. Experimental results reveal that our method enables accurate and computationally efficient RL extraction with considering return current distribution.

Web of Science

Language：English   Publishing type：Research paper (international conference proceedings)  

On-chip global signaling whose performance improves with technology advance is eagerly demanded. This work focuses on wave pipelining on on-chip transmission lines, which is one of probable solutions, and predicts the trend of signaling performance in the future. Experiments reveal that transmission capacity per channel will improve till at least 35nm technology in 10mm-long or below signaling. We also demonstrate that current-mode differential signaling is robust against power supply noise, but power delivery with non-zero impedance degrades the performance. © 2005 IEEE.

DOI： 10.1109/EPEP.2005.1563706

Scopus

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.

Web of Science

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English   Publishing type：Research paper (scientific journal)   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper discusses the frequency to extract RLC values from interconnects. In circuit design, frequency-independent equivalent circuit is widely used, and many design and analysis techniques based on this equivalent circuit are proposed so far. However in reality, characteristics of interconnects are frequency-dependent. Also pulse waveforms in digital circuits contain multiple frequency components. The frequency used for RLC extraction affects the accuracy of interconnect characterization, and hence careful determination of extraction frequency is critical. We propose a representative frequency for RLC extraction. Conventionally, representative frequencies are determined by input pulse. The proposed method decides the representative frequency based on the interconnect length, whereas conventional representative frequencies are determined by input pulse shape, period and patterns. We verify that the extraction at the proposed frequency provides the most accurate transition waveform against various input signals and interconnect structures in digital circuits.

DOI： 10.1093/ietfec/e88-a.4.885

Web of Science

Language：Japanese   Publishing type：Master’s thesis  

Language：Japanese   Publishing type：Master’s thesis  

Language：English  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：Japanese   Publishing type：Research paper (scientific journal)   Participation form：Joint(The main charge)  

Language：English   Publishing type：Research paper (international conference proceedings)  

Language：Japanese   Publishing type：Research paper (scientific journal)  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：English  

Language：Japanese   Publishing type：Research paper (conference, symposium, etc.)  

Language：Japanese  

J-GLOBAL

Language：Japanese  

Language：Japanese  

Language：Japanese  

CiNii Books

J-GLOBAL

Language：Japanese  

Language：Japanese  

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

A bandwidth enhancement technique for TransImpedance Amplifier (TIA) is proposed. Bandwidth is an important issue for CMOS high-speed amplifier and inductive peaking is a common practice for bandwidth enhancement. On the other hand, on-chip inductors occupy large area. We propose a inductive peaking with mutually coupled inductors. The mutualy coupled inductors integrates two inductors without area penalty. Experimental results show that the proposed method improves the bandwidth by 9% compared with conventional shunt peaking.

CiNii Books

J-GLOBAL

Language：Japanese  

J-GLOBAL

Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

This paper reports measurement results of on-chip interconnects with CMP dummy fill. CMP dummy fill is a floating metal for metal density adjustment. Conventionally, the effect of dummy fill on the interconnect characteristics is discussed mainly from the viewpoint of the capacitance. However in high frequency above 10GHz, the eddy current induced in dummy fills affects the interconnect loss. We fabricated test structures of on-chip interconnect with dummy fills. From the measurement results, the effect of the dummy fills on the wire resistance is not negligible even if the ground wires are adjacent to the signal wire. The dummy fills in the upper/lower metal layer affect the wire resistance and the resistance increases by 20% at 50GHz.

CiNii Books

Language：Japanese  

J-GLOBAL

Language：Japanese  

J-GLOBAL

Language：Japanese  

J-GLOBAL

Language：Japanese  

J-GLOBAL

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Event date： 2023.10

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Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：愛媛県男女共同参画センター  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：大阪大学豊中キャンパス  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：早稲田大学  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：早稲田大学  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：早稲田大学  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：大阪  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：大阪  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：金沢大学  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：東京電機大学  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：東京電機大学  

Language：Japanese   Presentation type：Oral presentation (general)  

Venue：日立製作所 研究開発グループ　生産イノベーションセンタ  

Language：Japanese   Presentation type：Poster presentation  

Venue：滋賀県立大学  

Language：Japanese   Presentation type：Poster presentation  

Venue：滋賀県立大学  

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Poster presentation  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Poster presentation  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

Language：Japanese   Presentation type：Symposium, workshop panel (nominated)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Symposium, workshop panel (nominated)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

Language：Japanese   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Symposium, workshop panel (nominated)  

Language：English   Presentation type：Symposium, workshop panel (nominated)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (invited, special)  

Language：English   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Poster presentation  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Poster presentation  

Language：English   Presentation type：Poster presentation  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：English   Presentation type：Oral presentation (general)  

Language：Japanese   Presentation type：Oral presentation (general)