Updated on 2024/11/15

写真a

 
TSUCHIYA Akira
 
Organization
Faculty of Advanced Engineering
Department
School of Engineering Department of Electronic Systems Engineering
Title
Associate Professor

Message

  • My research activity is mainly on high-frequency analog CMOS. Besides that, I am working on open-source IC design to realize a society that everyone can design integrated circuits.

Education

  • Kyoto University   Graduate School, Division of Information and Communication   Department of Communications and Computer Engineering

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    Course completed: Doctor's Course

    Country: Japan

  • Kyoto University   Graduate School, Division of Information and Communication   Department of Communications and Computer Engineering

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    Course completed: Master's Course

    Country: Japan

  • Kyoto University   Faculty of Engineering   Department of Electric and Electronic Engineering

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    Country: Japan

Degree

  • Ph. D. (Informatics) ( 2005.11   Kyoto University )

  • 修士(情報学) ( 2003.3   京都大学 )

  • 学士(工学) ( 2001.3   京都大学 )

Research Field

  • Integrated Circuit

Research Experience

  • The University of Shiga Prefecture   School of Engineering Department of Electronic Systems Engineering   Associate Professor

    2017.4

  • Kyoto University   Graduate School of Informatics   Assistant Professor

    2007.4 - 2017.3

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    Country:Japan

  • Kyoto University   Graduate School of Informatics   Research Assistant

    2005.12 - 2007.3

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    Country:Japan

  • 日本学術振興会   日本学術振興会特別研究員

    2004.4 - 2005.11

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    Country:Japan

Association Memberships

  • The Institute of Electronics, Information and Computer Engineers

    2002.4

  • The Institute of Electrical and Electronics Engineers

    2002.4

Research Areas

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment

Available Technology

  • アナログCMOS集積回路の設計技術と応用技術の研究

Papers

  • Cryogenic and RF Modeling of On-Chip Passive Devices for Quantum Computer Invited Reviewed

    Akira Tsuchiya

    IEEE 17th International Conference on Solid-State and Integrated Circuit Technology   1 - 3   2024.10

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    Authorship:Lead author, Last author, Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)  

  • Activities for Open-Source Integrated Circuits Design in Japan Invited Reviewed

    Akira Tsuchiya

    130 - 133   2024.6

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    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  • Mean-Free-Path-Based Evaluation of Size Effectand Anomalous Skin Effect in On-Chip Interconnects under Cryogenic Environment Reviewed

    Akira Tsuchiya

    28th IEEE Workshop on Signal and Power Integrity   1 - 4   2024.5

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    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  • A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks Reviewed International journal

    Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

    Microelectronics Journal   2024.3

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    Language:English   Publishing type:Research paper (scientific journal)   Participation form:Joint(The vice charge)  

    DOI: 10.1016/j.mejo.2024.106120

  • A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip Reviewed

    T. Inoue, A. Tsuchiya, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura

    IEEE Transactions on Circuits and Systems II   2024

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1109/TCSII.2024.3376200

  • High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS Invited Reviewed

    Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

    IEEE 15th International Conference on ASIC   2023.10

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    Authorship:Lead author   Language:English   Publishing type:Research paper (international conference proceedings)  

  • 4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS Reviewed

    Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

    The 20th International SoC Conference (ISOCC)   2023.10

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    Language:English   Publishing type:Research paper (international conference proceedings)  

  • Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process Reviewed

    Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

    IEICE Electronics Express   20 ( 18 )   2023.9

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1587/elex.20.20230339

  • 10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks Reviewed

    Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

    IEICE Electronics Express   20 ( 14 )   2023.7

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    Language:English   Publishing type:Research paper (scientific journal)  

    DOI: 10.1587/elex.20.20230238

  • A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS Reviewed

    T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura

    IEEE International Conference on Electronics, Circuits and Systems (ICECS)   1 - 4   2023

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    Language:English   Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/ICECS58634.2023.10382799

  • 4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS Reviewed

    D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya and K. Kishine

    International SoC Design Conference (ISOCC)   13 - 14   2023

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    Language:English   Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/ISOCC59558.2023.10396067

  • A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS Reviewed International journal

    Inoue T., Tsuchiya A., Kishine K., Ito D., Takahashi Y., Nakamura M.

    ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings   1 - 4   2022.10

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings   Participation form:Joint(The vice charge)  

    A burst-mode transimpedance amplifier (TIA) receives burst signals, which are intermittent signals. To reduce the power consumption during the idle times, we propose a burst-mode TIA with automatic power saving in 65-nm CMOS. It enables to provide a stable operation without a DC wander effect while receiving the burst signal. The post-layout simulation results show that the designed TIA can automatically reduce the power consumption during the idle times by 54.2% compared to that during the active times.

    DOI: 10.1109/ICECS202256217.2022.9970848

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  • A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band Reviewed International journal

    Inoue M., Nakashioya S., Inoue T., Tsuchiya A., Kishine K.

    ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings   1 - 4   2022.10

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings  

    Recently, radio-wave sensors have been utilized in automotive radar and biological sensing applications. Although beamforming using an array antenna is effective method for changing the radiation directivity, the phase-shift error causes degradation of the directivity significantly. In this paper, we propose a fine-tuning phase shifter with a vector synthesizer, which enables to control the phase-shift amount continuously in 24-GHz band. From the measurement results of the fabricated phase shifter using 65-nm CMOS technology, the variable phase-shift amount over a range of 360◦ is obtained continuously. In addition, the estimated radiation patterns show that the phase-shift and amplitude errors of the fabricated phase shifter are acceptable.

    DOI: 10.1109/ICECS202256217.2022.9970921

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  • A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA Reviewed International journal

    Okamoto M., Inoue T., Tsuchiya A., Kishine K.

    Proceedings - International SoC Design Conference 2022, ISOCC 2022   55 - 56   2022.10

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Proceedings - International SoC Design Conference 2022, ISOCC 2022   Participation form:Joint(The vice charge)  

    We propose a method for implementing an LSTM-based multiple-people identification system on a small-scale FPGA. To reduce the hardware-resource usage, we introduce a digit adjustment and bit reduction method for converting the floating-point type to the fixed-point type with high precision. It enables not only to reduce the hardware-resource usage without degrading the identification accuracy but also to shorten the computation time by 50% compared to that of the conventional floating-point type.

    DOI: 10.1109/ISOCC56007.2022.10031374

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  • Smart Computational Resource Distribution System with Automatic Classification Interface for CPS Reviewed International journal

    Teramura Y., Inoue T., Tsuchiya A., Kishine K.

    Proceedings - International SoC Design Conference 2022, ISOCC 2022   101 - 102   2022.10

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    This paper describes a proposal for a classification interface for computational resources distribution in CPS. The classification interface enables to distribute processing to the different computational resources (CPU and FPGA) automatically depending on the type of the processing. As a result, the total processing time is shortened by 50.9% compared to that of the system without the classification interface.

    DOI: 10.1109/ISOCC56007.2022.10031427

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  • Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing Reviewed International journal

    Shimohane S., Inoue T., Tsuchiya A., Kishine K.

    Proceedings - International SoC Design Conference 2022, ISOCC 2022   338 - 339   2022.10

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    In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAMbased system.

    DOI: 10.1109/ISOCC56007.2022.10031293

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  • A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS Reviewed International journal

    T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura

    65th IEEE International Midwest Symposium on Circuits and Systems   1 - 4   2022.8

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE   Participation form:Joint(The vice charge)  

    DOI: 10.1109/MWSCAS54063.2022.9859338

  • A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad Reviewed International journal

    A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura

    IEEE 65th International Midwest Symposium on Circuits and Systems   1 - 4   2022.8

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE   Participation form:Joint(The main charge)  

    DOI: 10.1109/MWSCAS54063.2022.9859435

  • Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit Reviewed

    Takahashi Y., Ito D., Namamura M., Tsuchiya A., Inoue T., Kishine K.

    Electronics (Switzerland)   11 ( 6 )   2022.3

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:Electronics (Switzerland)  

    In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dBΩ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 µm × 225 µm.

    DOI: 10.3390/electronics11060854

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  • Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion Reviewed International journal

    Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine

    International Conference on Electronics, Information, and Communication   579 - 582   2022.2

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEIE   Participation form:Joint(The vice charge)  

  • A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver Reviewed International journal

    Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine

    International Conference on Electronics, Information, and Communication   644 - 647   2022.2

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEIE   Participation form:Joint(The vice charge)  

  • Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems Reviewed International journal

    Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine

    International Conference on Electronics, Information, and Communication   616 - 619   2022.2

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEIE   Participation form:Joint(The vice charge)  

  • Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier Reviewed International journal

    Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, and Makoto Nakamura

    International Conference on Electronics, Information, and Communication   640 - 643   2022.2

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEIE   Participation form:Joint(The main charge)  

  • Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS Reviewed International journal

    Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

    The 27th Asia and South Pacific Design Automation Conference   96 - 97   2022.1

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:ACM   Participation form:Joint(The vice charge)  

  • A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks Reviewed International journal

    T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

    28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)   1 - 6   2021.11

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE   Participation form:Joint(The vice charge)  

    DOI: 10.1109/ICECS53924.2021.9665522

  • Dynamic Memory Access Control for Accelerating FPGA-based Image Processing Reviewed International journal

    Kenta Nishiguchi, Toshiyuki Inoue, Rei Yamazaki, Kazunori Ogohara, Akira Tsuchiya, Keiji Kishine

    Journal of Semiconductor Technology and Science   21 ( 1 )   29 - 38   2021.2

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEIE   Participation form:Joint(The vice charge)  

    DOI: 10.5573/JSTS.2021.21.1.029

  • 5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS Reviewed

    Ichii Y., Inoue T., Tsuchiya A., Kishine K.

    2021 International Conference on Electronics, Information, and Communication, ICEIC 2021   2021.1

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:2021 International Conference on Electronics, Information, and Communication, ICEIC 2021  

    This paper proposes a 5-Gb/s four-level pulse amplitude modulation (PAM4) transmitter using compensation circuit in data transmission systems. In PAM4 systems, the signal amplitude requires smaller rising and falling times. To achieve this, we adopted an analog feed forward equalizing (FFE) for the compensation in PAM4 transmitter. To confirm the advantage of the proposed technique, we fabricated a 5-Gb/s PAM4 transmitter IC in an 180-nm CMOS process for this work. The measured rising and falling times were 18% and 13% smaller than those without FFE, respectively.

    DOI: 10.1109/ICEIC51217.2021.9369819

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  • Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA Reviewed

    Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

    2021 International Conference on Electronics, Information, and Communication, ICEIC 2021   2021.1

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:2021 International Conference on Electronics, Information, and Communication, ICEIC 2021  

    Regression and classification are necessary for biometric systems and carried out using machine learning. A method for regression and classification is long short-term memory (LSTM). We proposed and implemented algorithms for low-energy LSTM for the regression of microwave-sensor signals into a small-scale FPGA. We found that our FPGA-based parallel (including unrolled)-pipelined algorithm decreased the computation time by 95% compared with the FPGA-based sequential algorithm. In addition, the amount of energy consumption with the proposed algorithm was reduced by 92% and 91% compared with that with a high-end GPU and CPU, respectively.

    DOI: 10.1109/ICEIC51217.2021.9369806

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  • Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers Reviewed International journal

    Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

    Asia-South Pacific Design Automation Conference   15 - 16   2021.1

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:ACM   Participation form:Joint(The vice charge)  

    DOI: 10.1145/3394885.3431646

  • A Method for Accelerating the Inference Process of FPGA-based LSTM for Biometric Systems Reviewed

    Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

    IEIE Transactions on Smart Processing and Computing   10 ( 5 )   416 - 423   2021.1

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEIE Transactions on Smart Processing and Computing  

    Biometric systems require the regression and classification of biological sensing data, which are both carried out using machine learning. Long short-term memory (LSTM) is one of the most common methods used for regression and classification. We have developed and implemented a low-energy LSTM algorithm for the regression of microwave sensor signals in a small-scale FPGA. Experimental results show that the FPGA-based parallel-pipelined unrolled algorithm can reduce the computation time by 95% compared to an FPGA-based sequential algorithm. In addition, we found that the power consumption can be reduced by 92% and 91% compared to that obtained with a high-end GPU and CPU, respectively.

    DOI: 10.5573/IEIESPC.2021.10.5.416

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  • Processing Time Reduction for JPEG Compression Using Pixel Array Conversion Reviewed International journal

    Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

    17th International SoC Design Conference   2020.10

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  • Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Reviewed International journal

    Akira TSUCHIYA, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, Hidetoshi ONODERA

    IEiCE Transactions on Electronics   E103-C ( 10 )   489 - 496   2020.10

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE   Participation form:Joint(The main charge)  

  • Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking Invited Reviewed International journal

    Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

    2020 IEEE International Symposium on Radio-Frequency Integration Technology   12 - 14   2020.9

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE   Participation form:Joint(The main charge)  

  • Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS Reviewed

    Inoue T., Tsuchiya A., Kishine K.

    Journal of Semiconductor Technology and Science   20 ( 2 )   177 - 186   2020.4

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:Journal of Semiconductor Technology and Science   Participation form:Joint(The vice charge)  

    © 2020, Institute of Electronics Engineers of Korea. All rights reserved. We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, band-width, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-mm CMOS type.

    DOI: 10.5573/JSTS.2020.20.2.177

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  • Capacitive Sensor for Contact Angle Estimation of Droplet on Microfluidic Chip Reviewed International journal

    Akira Tsuchiya, Toshiyuki Inoue and Keiji Kishine

    2019 Asia-Pacific Microwave Conference   2019.12

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  • Frequency Discriminator Using a Simple AD Converter for Interface Systems Reviewed International journal

    Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

    16th International SoC Design Conference   2019.10

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  • Optimization Technique of Memory Traffic for FPGA-Based Image Processing System Reviewed International journal

    Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara and Keiji Kishine

    16th International SoC Design Conference   2019.10

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  • Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS Reviewed International journal

    Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

    16th International SoC Design Conference   2019.10

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  • A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Reviewed International journal

    Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

    32nd International System-on-Chip Conference   2019.9

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE   Participation form:Joint(The main charge)  

  • Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier Reviewed International journal

    Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine

    32nd IEEE International System-on-Chip Conference   2019.9

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE   Participation form:Joint(The vice charge)  

  • Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity Reviewed

    Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA

    IEICE TRANSACTIONS on Electronics   E102-C ( 7 )   573 - 579   2019.7

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:IEICE   Participation form:Joint(The main charge)  

    DOI: 10.1587/transele.2018CTP0007

  • FPGA-based binary labeling signal transmission system Reviewed

    Inoue T., Nomura K., Noguchi R., Koda N., Tsuchiya A., Kishine K.

    Journal of Semiconductor Technology and Science   19 ( 3 )   276 - 286   2019.6

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:Journal of Semiconductor Technology and Science  

    © 2019, Institute of Electronics Engineers of Korea. All rights reserved. We implemented and evaluated our newly developed binary labeling signal transmission system using field-programmable gate arrays. In this system, the state of “0” or “1” of labeling signals is related to modulation or non-modulation of frame signals, and the labeling signals can be multiplexed to frame signals and transmitted without changing the configuration of the original frame signal. We designed a modulation-system protocol for implementing the above system and propose a digital smoothing technique for stabilizing a phase-locked loop circuit. We verified that our digital smoothing technique prevents bit error of the modulated frame signals in the implemented transmitter. The labeling signal multiplexed to the frame signals is demodulated without bit error in the implemented transceiver.

    DOI: 10.5573/JSTS.2019.19.3.276

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  • A 25-Gb/s Low-Power Clock and Data Recovery with an ActiveStabilizing CML-CMOS Conversion Reviewed International journal

    Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

    The 25th IEEE International Conference on Electronics Circuits and Systems   2018.12

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE   Participation form:Joint(The vice charge)  

  • A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-less Bandwidth Compensation Reviewed International journal

    Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

    IEEE Asian Solid-State Circuits Conference   69 - 72   2018.11

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  • Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback Reviewed International journal

    Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, and Hidetoshi Onodera

    The 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2018)   2018.8

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  • Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net Reviewed International journal

    Akira TSUCHIYA, Akitaka HIRATSUKA, Toshiyuki INOUE, Keiji KISHINE, Hidetoshi ONODERA

    IEEE Workshop on Signal and Power Integrity   1 - 4   2018.5

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  • A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS Reviewed International journal

    Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka

    International Symposia on VLSI Design, Automation and Test   2018.4

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  • Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS Reviewed International journal

    Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura

    International SoC Design Conference   2017.11

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  • FPGA-Based Transceiver Circuit for Labeling Signal Transmission System Reviewed International journal

    Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

    International SoC Design Conference   2017.11

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  • Compact Implementation IIR Filter in FPGA for Noise Reduction of Sensor Signal Reviewed International journal

    Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

    International SoC Design Conference   2017.11

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  • Power-Bandwidth Trade-Off Analysis of Multi-Stage Inverter-Type Transimpedance Amplifier for Optical Communication Reviewed International journal

    Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera

    MWSCAS2017   2017.8

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  • A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS Reviewed International journal

    T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto

    IEIE Transactions on Smart Signal and Computing   5 ( 3 )   207 - 214   2016.6

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  • A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS Reviewed

    T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto

    IEIE Transactions on Smart Signal and Computing   5 ( 3 )   207 - 214   2016.6

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  • A 32-Gb/s output buffer circuit with doubled pre-emphasis in 65-nm CMOS Reviewed

    T. Tanaka, K. Kishine, D. Omoto, A. Tsuchiya, H. Inaba

    International Conference on Electronics, Information, and Communication   2016.1

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  • A 25-Gb/s 480-mW CMOS Modulator Driver Using Area-Efficient 3D Inductor Peaking Reviewed

    Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura

    IEEE Asian Solid-State Circuits Conference   2015.11

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    DOI: 10.1109/ASSCC.2015.7387470

  • A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage Reviewed

    N. Kamae, A. Tsuchiya, H. Onodera

    IEICE Transactions on Electronics   98-C ( 6 )   504 - 511   2015.6

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  • A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage Reviewed

    Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

    IEICE TRANSACTIONS ON ELECTRONICS   E98C ( 6 )   504 - 511   2015.6

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    A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5V to 1.2V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65 nm CMOS process. Area of the AES core is 0 : 22 mm(2) and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5V to 1.2V which enables the reduction of power dissipation, for example, of 17% at 400MHz operation.

    DOI: 10.1587/transele.E98.C.504

    Web of Science

  • Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS Reviewed

    K. Kishine, H. Inaba, H. Inoue, M. Nakamura, A. Tsuchiya, H. Katsurai, H. Onodera

    IEEE Transactions on Circuits and Systems I   62 ( 5 )   1288 - 1295   2015.5

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  • A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS Reviewed

    Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS   62 ( 5 )   1288 - 1295   2015.5

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    A multi-rate burst-mode clock and data recovery ( BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW.

    DOI: 10.1109/TCSI.2015.2416812

    Web of Science

  • A wireless neural recording system with a precision motorized microdrive for freely behaving animals Reviewed International journal

    T. Hasegawa, H. Fujimoto, K. Tashiro, M. Nonomura, A. Tsuchiya, D. Watanabe

    Scientific Reports   5 ( 7853 )   2015.1

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  • A wireless neural recording system with a precision motorized microdrive for freely behaving animals Reviewed

    Taku Hasegawa, Hisataka Fujimoto, Koichiro Tashiro, Mayu Nonomura, Akira Tsuchiya, Dai Watanabe

    SCIENTIFIC REPORTS   5   7853   2015.1

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    The brain is composed of many different types of neurons. Therefore, analysis of brain activity with single-cell resolution could provide fundamental insights into brain mechanisms. However, the electrical signal of an individual neuron is very small, and precise isolation of single neuronal activity from moving subjects is still challenging. To measure single-unit signals in actively behaving states, establishment of technologies that enable fine control of electrode positioning and strict spike sorting is essential. To further apply such a single-cell recording approach to small brain areas in naturally behaving animals in large spaces or during social interaction, we developed a compact wireless recording system with a motorized microdrive. Wireless control of electrode placement facilitates the exploration of single neuronal activity without affecting animal behaviors. Because the system is equipped with a newly developed data-encoding program, the recorded data are readily compressed almost to theoretical limits and securely transmitted to a host computer. Brain activity can thereby be stably monitored in real time and further analyzed using online or offline spike sorting. Our wireless recording approach using a precision motorized microdrive will become a powerful tool for studying brain mechanisms underlying natural or social behaviors.

    DOI: 10.1038/srep07853

    Web of Science

  • Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation Reviewed

    Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

    PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015)   181 - 185   2015

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    Energy-efficiency has become the driving force of today's LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.

    DOI: 10.1109/ISQED.2015.7085421

    Web of Science

  • PLL の物理レイアウト自動生成を目指した設計手法 Reviewed

    釡江典裕, 土谷亮, 石原亨, 小野寺秀俊

    情 報処理学会DA シンポジウム   2014.8

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  • Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure Reviewed

    SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

    IEICE TRANSACTIONS ON ELECTRONICS   E97C ( 4 )   325 - 331   2014.4

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    This paper proposes a radiation-hardened phase-locked loop (RH-PLL) with a switchable dual modular redundancy (DMR) structure. After radiation strikes, unhardened PLLs suffer clock perturbations. Conventional RH-PLLs have been proposed to reduce recovery time after perturbation. However, this recovery still requires tens of clock cycles. Our proposal involves 'detecting' and 'switching', rather than 'recovering' from clock perturbation. Detection speed is crucial for robust perturbation-immunity. We identify types of clock perturbation and then propose a set of detectors to detect each type. With this method, the detectors guarantee high-speed detection that leads to perturbation-immune switching from a radiated clock to an undistorted clock. The proposed RH-PLL was fabricated and then verified with a radiation test on real silicon.

    DOI: 10.1587/transele.E97.C.325

    Web of Science

  • Analysis of radiation-induced clock-perturbation in phase-locked Loop Reviewed

    S.N. Kim, A. Tsuchiya, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96-A ( 3 )   768 - 776   2014.3

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  • A body bias generator with low supply voltage for within-die variability compensation Reviewed

    N. Kamae, A. Tsuchiya, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E96-A ( 3 )   734 - 740   2014.3

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  • A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation Reviewed

    Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E97A ( 3 )   734 - 740   2014.3

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    A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and Power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6 V to 1.2 V. We fabricated the BBG in a 65 nm CMOS process to control 0.1 mm(2) of core circuit with the area overhead of 1.4% for the BBG.

    DOI: 10.1587/transfun.E97.A.734

    Web of Science

  • Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop Reviewed

    SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E97A ( 3 )   768 - 776   2014.3

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    This paper presents an analysis of radiation-induced clock-perturbation in phase-locked loop (PLL). Due to a trade-off between cost, performance, and reliability, radiation hardened PLL design need robust strategy. Thus, evaluation of radiation vulnerability is important to choose the robust strategy. The conventional evaluation-method is however based on brute-force analysis - SPICE simulation and experiment. The presented analysis result eliminates the brute-force analysis in evaluation of the radiation vulnerability. A set of equations enables to predict the radiation-induced clock-perturbation at the every sub-circuits. From a demonstration, the most vulnerable nodes have been found, which are validated using a PLL fabricated with 0.18 mu m CMOS process.

    DOI: 10.1587/transfun.E97.A.768

    Web of Science

  • Radiation-hardened PLL with a switchable dual modular redundancy structure Reviewed

    S.N. Kim, A. Tsuchiya, H. Onodera

    IEICE Transactions on Electronics   E97-C ( 4 )   325 - 331   2014.1

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  • 25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS Reviewed

    Tomoki Tanaka, Keiji Kishine, Hiromi Inaba, Akira Tsuchiya

    2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)   94 - 95   2014

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    A 25-Gb/s inductorless output buffer circuit with a pre-emphasis is proposed. We designed the circuit parameters according to the frequency characteristics of the emphasized signal. To confirm the advantages of the emphasis circuit, we fabricated an output buffer IC in a 65-nm CMOS process. The proposed circuit has a control voltage to adjust the emphasis amplitude according to the load outside the chip. Measurement results showed that the jitters were 40% lower with the emphasis circuit than without, indicating that our proposed configuration can be applied to the design of output buffer circuits for higher operation speed.

    DOI: 10.1109/ISOCC.2014.7087578

    Web of Science

  • A Body Bias Generator with Wide Supply-Range down to Threshold Voltage for Within-Die Variability Compensation Reviewed

    Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Hidetoshi Onodera

    2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)   53 - 56   2014

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    A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. While FGBB is effective in reducing variability and power consumption, a number of BBGs are required on a die and therefore simplified design of BBGs is necessary. This paper proposes a cell-based design of a BBG that generates forward and reverse body bias voltages only from a core supply voltage ranging from the near threshold of 500mV to the nominal voltage of 1.2V. This wide operating range is achieved by a low voltage error amplifier with a V-th biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm low power CMOS process to control 0.22mm(2) of core circuit with the area overhead of 2.3% for the BBG.

    DOI: 10.1109/ASSCC.2014.7008858

    Web of Science

  • A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops Reviewed

    Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai

    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)   2704 - 2707   2014

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    A 12.5-Gb/s burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops which operate complementarily. The same type of circuit configurations are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a 12.5-Gb/s-BCDR IC with the 65-nm-MOSFET process. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gis. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW, respectively.

    DOI: 10.1109/ISCAS.2014.6865731

    Web of Science

  • \Analysis of Radiation-Induced Timing Vulnerability on Phase- locked Loops Reviewed

    S.N. Kim, A. Tsuchiya, H. Onodera

    情報処理学会DA シンポジウム   2013.8

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  • A 25-Gb/s LD Driver with Area-Effective Inductor in a 0.18-mu m CMOS Reviewed

    Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

    2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)   105 - 106   2013

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    This paper presents high-speed and area-efficient laser-diode driver with interwoven inductor in a 0.18-mu m CMOS. We interweave ten peaking inductors for area-effective implementation as well as performance enhancement. Interwoven inductor can not only achieve area-efficiency but also tune frequency characteristic. Mutual inductances of interwoven inductor enhance bandwidth and suppress group delay dispersion. The test chip area is 0.32 mm(2) and the maximum operating speed is 25 Gb/s.

    DOI: 10.1109/ASPDAC.2013.6509578

    Web of Science

  • Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    IMFEDK 2013 - 2013 International Meeting for Future of Electron Devices, Kansai   106 - 107   2013

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    This paper discusses loss of on-chip transmission-line in terahertz region. Above 100 GHz, modeling of on-chip transmission-line is an important issue. We evaluate the impact of eddy current and anomalous skin effect by a field solver. Simulation results show that eddy current in dummy fills has higher impact of 10% on transmission-line loss. Anomalous skin effect is not negligible, but its impact is about 5% at 100 GHz. © 2013 IEEE.

    DOI: 10.1109/IMFEDK.2013.6602261

    Scopus

  • Advanced RF and analog integrated circuits for fourth generation wireless communications and beyond Reviewed

    Ramesh Pokharel, Leonid Belostotski, Akira Tsuchiya, Ahmed Allam, Mohammad S. Hashmi

    International Journal of Microwave Science and Technology   2013

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    DOI: 10.1155/2013/272070

    Scopus

  • A slow-wave transmission line with thin pillars for millimeter-wave CMOS Reviewed

    Taro Amagai, Akira Tsuchiya, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera

    2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013   2013

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    This paper presents a slow-wave transmission line with thin pillars on strips shield. Slow-wave transmission lines are mostly used as stub filters. The proposed structure with pillars has higher capacitance and inductance per unit length of the line. Thus, high phase constant and quality factor can be achieved. We compare simulation results between the proposed structure and conventional lines for millimeter-wave CMOS. The proposed line gives higher phase constant of 3.1 rad/mm and high quality factor of 21.6 at 60 GHz. © 2013 IEEE.

    DOI: 10.1109/SaPIW.2013.6558341

    Scopus

  • Perturbation-immune radiation-hardened PLL with a switchable DMR structure Reviewed

    Sin Nyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

    Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013   128 - 132   2013

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    This paper proposes a perturbation-immune radiation-hardened PLL with a switchable dual modular redundancy (DMR) structure. By a radiation-strike, a PLL has clock-perturbation for a while. Conventional RHPLLs are proposed to reduce recovery-time which is the time to recover from perturbation. However, recovery still needs tens of clock cycles. Our proposal is 'detecting' and 'switching' instead of 'recovering' clock-perturbation. For robust perturbation-immunity, detecting speed is important. We identify types of clock-perturbation and-then propose a set of detectors to detect each type. With this, detectors guarantee high speed in detection. © 2013 IEEE.

    DOI: 10.1109/IOLTS.2013.6604063

    Scopus

  • Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation Reviewed International journal

    A. K. M. Mahfuzul Islam, A. Tsuchiya, K. Kobayashi, H. Onodera

    IEEE Transactions on Semiconductor Manufacturing   25 ( 4 )   571 - 580   2012.11

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  • A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation Reviewed

    Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

    IEEE Asian Solid-State Circuits Conference(A-SSCC) 2012, pp. 389-392, Nov 2012.   2012.11

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  • Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation Reviewed

    Islam A. K. M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING   25 ( 4 )   571 - 580   2012.11

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    This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation.

    DOI: 10.1109/TSM.2012.2198677

    Web of Science

  • Dual-PLL based on Temporal Redundancy for Radiation-Hardening Reviewed

    SinNyoung KIM, Akira TSUCHIYA, Hidetoshi ONODERA

    Proceedings of 10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications   2012.10

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  • Modeling of Single-Event Failures in Dividerand PFD of PLLs based on Jitter Analysis Reviewed

    SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

    13th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2012.   2012.9

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  • チップ内基板バイアス生成回路のモジュール化設計 Reviewed

    釡江典裕, 土谷亮, 小野寺秀俊

    情報処理学会DAシンポジウム2012論文集, pp. 55-60, Aug 2012.   2012.8

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  • Area-effective inductive peaking with interwoven inductor for high-speed laser-diode driver for optical communication system Reviewed

    T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E95-A ( 2 )   479 - 486   2012.2

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  • Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System Reviewed

    Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E95A ( 2 )   479 - 486   2012.2

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    This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 mu m CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

    DOI: 10.1587/transfun.E95.A.479

    Web of Science

  • A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18μm CMOS Reviewed

    T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   561 - 562   2012

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    DOI: 10.1109/ASPDAC.2012.6165018

  • Impact of radiation loss in on-chip transmission-line for terahertz applications Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    2012 IEEE 16th Workshop on Signal and Power Integrity, SPI 2012 - Proceedings   125 - 128   2012

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    This paper discusses radiation loss of on-chip transmission-line. Since terahertz applications of integrated circuits are emerging, precise modeling in terahertz region is needed. We evaluate conductor loss, dielectric loss and radiation loss of on-chip transmission-line by a full-wave field solver. Simulation results show that design focusing conductor loss may cause large radiation loss in terahertz region. Quantitative evaluation of the impact of radiation loss is demonstrated. Also we show that thick signal wire and differential line is effective to reduce the loss. © 2012 IEEE.

    DOI: 10.1109/SaPIW.2012.6222926

    Scopus

  • A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μm CMOS Reviewed

    S. Miyawaki, M. Nakamura, A. Tsuchiya, K. Kishine, H. Onodera

    2011 International SoC Design Conference, ISOCC 2011   223 - 226   2011

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  • Gradient Resistivity Method for Numerical Evaluation of Anomalous Skin Effect Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    2011 15TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS (SPI)   139 - 142   2011

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    This paper discusses a method to evaluate anomalous skin effect. Anomalous skin effect (ASE) is a phenomenon which appears when the skin depth becomes comparable to the mean free path of electrons. In anomalous region, the effective resistivity depends on skin depth. Thus it is difficult to evaluate by field-solvers. The proposed method realizes field simulation considering ASE by gradient resistivity. Simulation result shows that the resistance increase more rapid than classical skin effect above 100GHz. The effect on the resistance is 5% at 100GHz and 10% at 300GHz.

    DOI: 10.1109/SPI.2011.5898859

    Web of Science

  • An area effective forward/reverse body bias generator for within-die variability compensation Reviewed

    Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

    2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011   217 - 220   2011

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    To compensate the die-to-die and location correlated variation, we propose to split digital circuit to sub-mm-scale area controlling each area with an on-chip forward/reverse body bias generator (BBG). The proposed BBG is configured as a feedforward control system to achieve small area. The BBG is realized by combining a low output resistance DAC and a charge pump type level shifter. The BBG design is implemented with 1.2V thin gate oxide MOSFET in a 65nm CMOS technology. The simulation and measurement results show that the variation is compensated with an area overhead as small as 2%. © 2011 IEEE.

    DOI: 10.1109/ASSCC.2011.6123641

    Scopus

  • Variation-sensitive monitor circuits for estimation of die-to-die process variation Reviewed

    I.A.K.M. Mahfuzul, A. Tsuchiya, K. Kobayashi, H. Onodera

    IEEE International Conference on Microelectronic Test Structures   153 - 157   2011

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    DOI: 10.1109/ICMTS.2011.5976878

  • レイアウト制約が性能と製造性に与える影響 Reviewed

    北島和彦, 砂川洋輝, 土谷亮, 小野寺秀俊, 小野寺秀俊

    情報処理学会DAシンポジウム論文集   2010 ( 7 )   221 - 226   2010.8

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  • Effect of regularity-enhanced layout on variability and circuit performance of standard cells Reviewed

    H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, H. Onodera

    IPSJ Transactions on System LSI Design Methodology   3   130 - 139   2010.2

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  • A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18-mu m CMOS Reviewed

    Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

    IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010   2010

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    A laser-diode (LD) driver with interwoven mutually-coupled peaking inductors for high-speed optical networks is presented. Six and four inductors are interwoven into two sets of inductors for area-effective implementation as well as performance enhancement. The proposed circuit is fabricated in CMOS 0.18-mu m process. The circuit area is 0.34mm(2) and the maximum operating speed is 16Gbps. Compared to a conventional LD driver in 0.18-mu m CMOS, the proposed circuit achieves 1.6 times faster operation, 26% smaller area with 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current.

    DOI: 10.1109/CICC.2010.5617416

    Web of Science

  • Effect of regularity-enhanced layout on variability and circuit performance of standard cells Reviewed

    Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

    IPSJ Transactions on System LSI Design Methodology   3   130 - 139   2010

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    As the minimum feature size shrinks down far below sub-wavelength, Design for Manufacturability or layout regularity plays an important role for maintaining pattern fidelity in photolithography. However, it also incurs overheads in circuit performances due to parasitic capacitance. In this paper, we examine the effect of layout regularity on printability and circuit performance by lithography simulation and transistor-level simulation. It is shown that regularity-enhanced cells provide better Critical Dimension (CD) stability under defocus and lead to delay increase. Then we evaluate the effect of layout regularity by a real chip measurement in 90 nm, 65 nm and 45 nm processes. For example, in a 65 nm process, inverter Ring Oscillators (ROs) that have the smallest poly pitch with dummy-poly insertion exhibits 19% reduction of WID and D2D variation with delay overhead of 2.5%, compared to the ROs without dummy-poly insertion. However, we have observed that the effect of layout regularity varies depending on fabrication processes and circuit structures. It is therefore important to obtain the best trade-off among performance overhead and variability reduction for each process technology. © 2010 Information Processing Society of Japan.

    DOI: 10.2197/ipsjtsldm.3.130

    Scopus

  • A design procedure of predictive RF MOSFET model for compatibility with ITRS Reviewed

    Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

    Proceedings - IEEE International SOC Conference, SOCC 2010   396 - 399   2010

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    A design procedure for generating predictive MOS-FET models is proposed. Due to evolving nature of future prediction, predictive models based on a certain prediction soon become absolute. We have therefore developed a design procedure for maintaining compatibility with most up-to-date prediction such as ITRS. The design procedure can generate predictive RF models for the first time. Details of the design procedure for BSIM4 as a core model are explained, with an application to LNA design example. © 2010 IEEE.

    DOI: 10.1109/SOCC.2010.5784704

    Scopus

  • A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-μm CMOS Reviewed

    T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

    Proceedings of the Custom Integrated Circuits Conference   2010

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    DOI: 10.1109/CICC.2010.5617416

  • Measurement of on-chip transmission-line with stacked split-ring resonators Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings   137 - 140   2010

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    This paper reports measurement results of on-chip transmission-line with split-ring resonators. Split-ring resonator (SRR) has attracted attention as an implementation of metamaterial (left-handed material). However when simple SRR is implemented in LSIs, the resonance frequency becomes around 200GHz and it is too high to employ on on-chip circuits. We designed a stacked SRR to lower the resonant frequency in a 0.18//m CMOS. Measurement results show that the stacked SRRs can realize the resonance frequency below 50GHz. Also measurement results show a guideline of area effective implementation of on-chip SRR. © 2010 IEEE.

    DOI: 10.1109/SPI.2010.5483544

    Scopus

  • Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability Reviewed

    A.K.M Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

    Tau Workshop 2010, Mar 2010.   2010

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  • Statistical gate delay model for multiple input switching Reviewed

    T. Fukuoka, A. Tsuchiya, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E92-A ( 12 )   3070 - 3078   2009.12

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  • Statistical Gate Delay Model for Multiple Input Switching Reviewed

    Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E92A ( 12 )   3070 - 3078   2009.12

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    In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the Output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80% error in worst case. The error of the proposed method is less than 20%.

    DOI: 10.1587/transfun.E92.A.3070

    Web of Science

  • チップ内ばらつきが順序セルの動作特性に与える影響 Reviewed

    砂川洋輝, 土谷亮, 小林和淑, 小野寺秀俊

    情報処理学会DA シンポジウム   2009.8

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  • Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells Reviewed

    Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

    ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2   195 - 200   2009

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    As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-off among manufacturability, cost, and performance for each process technology. This paper discusses the efiect of layout regularity on printability and circuit performance in 90 45nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows in a 45nm process. We demonstrate the quantitative evaluation of the trade-off between printability and circuit performance of regularity-enhanced standard cells.

    DOI: 10.1109/ISQED.2009.4810293

    Web of Science

  • High performance on-chip differential signaling using passive compensation for global communication Reviewed

    L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E.S. Kuh, C.-K. Cheng

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   385 - 390   2009

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    DOI: 10.1109/ASPDAC.2009.4796511

  • Effect of underlayer dummy fills on on-chip transmission line Reviewed

    A. Tsuchiya, H. Onodera

    2009 IEEE Workshop on Signal Propagation on Interconnects, SPI \\'09   2009

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    DOI: 10.1109/SPI.2009.5089867

  • On-Chip Metamaterial Transmission-Line Based on Stacked Split-Ring Resonator for Millimeter-Wave LSIs Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5   1458 - 1461   2009

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    This paper proposes a method to realize on-chip metamaterial transmission-line. Since the resonant frequency of split-ring resonator (SRR) depends on the size strongly, it is difficult to realize metamaterial transmission-line in integrated circuits. If we implement a conventional SRR to on-chip transmission-line, the resonant frequency is around 200GHz. We propose a stacked SRR using on-chip multi-layer interconnect. The stacked SRR is evaluated by a field-solver and the experimental results verify that the stacked SRR can realize the resonant frequency below 60GHz.

    DOI: 10.1109/APMC.2009.5384480

    Web of Science

  • Analytical eye-diagram model for on-chip distortionless transmission lines and its application to design space exploration Reviewed

    M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E91-A ( 12 )   3474 - 3480   2008.12

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  • Patterned floating dummy fill for on-chip spiral inductor considering the effect of dummy fill Reviewed International journal

    A. Tsuchiya, H. Onodera

    IEEE Transactions on Microwave Theory and Techniques   56 ( 12 )   3217 - 3222   2008.12

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  • Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration Reviewed

    Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E91A ( 12 )   3474 - 3480   2008.12

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    This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.

    DOI: 10.1093/ietfec/e91-a.12.3474

    Web of Science

  • Patterned Floating Dummy Fill for On-Chip Spiral Inductor Considering the Effect of Dummy Fill Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES   56 ( 12 )   3217 - 3222   2008.12

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    This paper discusses the effect of dummy fills on the performance of spiral inductors. In Si-CMOS processes that use copper wire, metal dummy fills are required to prevent thickness fluctuation in the chemical mechanical polishing stage. Dummy fills have been thought to affect the wire capacitance; however, in high frequency, dummy fills also affect the wire resistance and the wire inductance due to the eddy current in dummy fills. This work evaluates the effect of the dummy fills by three-dimensional field solver and proposes a structure to suppress the effect of dummy fills. Experimental results show that the proposed method can decrease the effect of dummy fills on the Q-factor by 83% compared with the conventional dummy fill insertion.

    DOI: 10.1109/TMTT.2008.2007362

    Web of Science

  • Accurate estimation of the worst-case delay in statistical static timing analysis Reviewed

    H. Terada, T. Fukuoka, A. Tsuchiya, H. Onodera

    IPSJ Transactions on System LSI Design Methodology   1   116 - 125   2008.8

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  • Accurate estimation of the worst-case delay in statistical static timing analysis Reviewed

    Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

    IPSJ Transactions on System LSI Design Methodology   1   116 - 125   2008.8

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    In this paper, we propose an approximation method for the statistical MAX operation such that it results in a normal distribution good for the worst-case delay analysis. The important operation in SSTA is SUM and MAX of distributions. In general, the delay variation is modeled as normal distribution. The result of SUM operation of two normal distributions is also normal distribution. On the other hand, the result of MAX operation is not normal distribution. Thus approximation to normal distribution is commonly used. We also explain that the proposed MAX operation at each gate also contributes to the accurate estimation in the worst-case delay analysis of the whole circuit. Experimental results show that the proposed method leads to a good approximation for a normal distribution resulted from MAX operation of normal distributions with and without correlation, and the approximation improves the accuracy of the worst-case delay analysis. In a circuit example, the errors of worst-case delay computed by the previous method are about 20%, and the errors computed by the proposed method are under 5%. © 2008 Information Processing Society of Japan.

    DOI: 10.2197/ipsjtsldm.1.116

    Scopus

  • リングオシレータアレイによるゲート遅延ばらつきの評価とモデル化 Reviewed

    寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

    情報処理学会DAシンポジウム論文集   2008 ( 7 )   199 - 204   2008.8

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    J-GLOBAL

  • レイアウト規則性が回路性能とばらつきに及ぼす影響の評価 Reviewed

    砂川洋輝, 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

    情報処理学会DAシンポジウム論文集   2008 ( 7 )   67 - 72   2008.8

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    J-GLOBAL

  • Dummy fill insertion considering the effect on high-frequency characteristics of spiral inductors Reviewed

    A. Tsuchiya, H. Onodera

    IEEE MTT-S International Microwave Symposium Digest   787 - 790   2008

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    DOI: 10.1109/MWSYM.2008.4632950

  • On-chip high performance signaling using passive compensation Reviewed

    Z. Yulei, Z. Ling, A. Tsuchiya, M. Hashimoto, C.-K. Cheng

    26th IEEE International Conference on Computer Design 2008, ICCD   182 - 187   2008

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    DOI: 10.1109/ICCD.2008.4751859

  • Statistical gate delay model for multiple input switching Reviewed

    T. Fukuoka, A. Tsuchiya, H. Onodera

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   286 - 291   2008

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    DOI: 10.1109/ASPDAC.2008.4483959

  • 同時スイッチングを考慮した統計的遅延解析 Reviewed

    福岡孝之, 土谷亮, 小野寺秀俊

    情報処理学会DAシンポジウム論文集   2007 ( 7 )   13 - 18   2007.8

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    J-GLOBAL

  • 統計的遅延解析における遅延分布間の最大値計算手法 Reviewed

    寺田晴彦, 福岡孝之, 土谷亮, 小野寺秀俊

    情報処理学会DAシンポジウム論文集   2007 ( 7 )   7 - 12   2007.8

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    J-GLOBAL

  • Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling Reviewed

    A. Tsuchiya, M. Hashimoto, H. Onodera

    IEICE Transactions on Electronics   E90-C ( 6 )   1267 - 1273   2007.6

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  • Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

    T. Kuboki, A. Tsuchiya, H. Onodera

    IEICE Transactions on Electronics   E90-C ( 6 )   1274 - 1281   2007.6

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  • Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

    Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera

    IEICE TRANSACTIONS ON ELECTRONICS   E90C ( 6 )   1274 - 1281   2007.6

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    This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip trans mission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

    DOI: 10.1093/ietele/e90-c.6.1274

    Web of Science

  • Analytical estimation of interconnect loss due to dummy fills Reviewed

    20   19 - 22   2007.4

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  • A 10Gbps/channel on-chip signaling circuit with an impedance-unmatched CML driver in 90nm CMOS technology Reviewed

    T. Kuboki, A. Tsuchiya, H. Onodera

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   120 - 121   2007

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    DOI: 10.1109/ASPDAC.2007.357970

  • Effect of dummy fills on high-frequency characteristics of on-chip interconnects Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006   275 - 278   2007

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    This paper discusses the effect of dummy fills on on-chip interconnect characteristics. The effect of dummy fills has been discussed from the viewpoint of the capacitance. However in high frequency, the magnetic coupling between the signal current and the eddy current in the dummy fills is not negligible. We evaluate the characteristics of on-chip interconnects with dummy fills by a 3D field solver. The size and the location of dummy fills are varied. We also evaluate the effect of dummy fills in the other interconnect layers. Experimental results shows that the impact of the dummy fills on the resistance and the attenuation is not negligible in high frequency such as 50GHz, and the dummy fills in the other layers have strong effect to the interconnect characteristics. The increase of the attenuation constant due to the dummy fills becomes 20% in maximum. ©2006 IEEE.

    DOI: 10.1109/SPI.2006.289243

    Scopus

  • Effect of Dummy Fills on High frequency characteristics of Spiral Inductor Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007), pp.256-260, Oct 2007.   2007

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  • Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration Reviewed

    Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

    Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007   869 - 872   2007

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    This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified. We also apply the proposed model to design trade-off analysis.

    DOI: 10.1109/CICC.2007.4405866

    Scopus

  • Measurement of interconnect loss due to dummy fills Reviewed

    Akira Tsuchiya, Hidetoshi Onodera

    2007 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS   241 - 244   2007

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    This paper reports measurement results of on-chip interconnects with CMP dummy fill. CMP dummy fill is a floating metal for metal density adjustment. In high frequency above 10GHz, the eddy current induced in dummy fills affects the interconnect loss. We fabricated test structures of on-chip interconnect with dummy fills. From the measurement results, the effect of the dummy fills on the wire resistance is not negligible even if the ground wires are adjacent to the signal wire. The dummy fills in the upper/lower metal layer affect the wire resistance and the resistance increases by 20% at 50GHz.

    DOI: 10.1109/SPI.2007.4512261

    Web of Science

  • Worst-case delay analysis considering the variability of transistors and interconnects Reviewed

    T. Fukuoka, A. Tsuchiya, H. Onodera

    Proceedings of the International Symposium on Physical Design   35 - 42   2007

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    DOI: 10.1145/1231996.1232006

  • Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

    T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

    Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006   227 - 230   2007

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    This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

    DOI: 10.1109/SPI.2006.289229

    Web of Science

  • Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

    T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 12 )   3560 - 3568   2006.12

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  • Interconnect RL extraction based on transfer characteristics of transmission-line Reviewed

    A. Tsuchiya, M. Hashimoto, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E89-A ( 12 )   3585 - 3593   2006.12

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    Language:English   Publishing type:Research paper (scientific journal)   Participation form:Joint(The main charge)  

  • Interconnect RL extraction based on transfer characteristics of transmission-line Reviewed

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 12 )   3585 - 3593   2006.12

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    This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. Experimental results show that the proposed method provides accurate transition waveforms over various interconnect topologies.

    DOI: 10.1093/ietfec/e89-a.12.3585

    Web of Science

  • Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

    Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E89A ( 12 )   3560 - 3568   2006.12

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    This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow. key words: substrate, interconnect, resistance, inductance, SoC

    DOI: 10.1093/ietfec/e89-a.12.3560

    Web of Science

  • トランジスタと配線構造のばらつきを考慮した遅延時間のワーストケース解析 Reviewed

    福岡孝之, 土谷亮, 小野寺秀俊

    情報処理学会DAシンポジウム論文集   2006 ( 7 )   13 - 18   2006.7

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    Language:Japanese   Publishing type:Research paper (conference, symposium, etc.)  

    J-GLOBAL

  • Performance prediction of on-chip high-speed signaling Reviewed

    19   393 - 398   2006.4

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  • Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

    19   387 - 392   2006.4

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  • Alternate self-shielding for high-speed and reliable on-chip global interconnect Reviewed

    Y. Yuyama, A. Tsuchiya, K. Kobayashi, H. Onodera

    IEICE Transactions on Electronics   E89-C ( 3 )   327 - 333   2006.3

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  • Alternate self-shielding for high-speed and reliable on-chip global interconnect Reviewed

    Y Yuyama, A Tsuchiya, K Kobayashi, H Onodera

    IEICE TRANSACTIONS ON ELECTRONICS   E89C ( 3 )   327 - 333   2006.3

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    In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.

    DOI: 10.1093/ietele/e89-c.3.327

    Web of Science

  • Analytical estimation of interconnect loss due to dummy fills Reviewed

    A. Tsuchiya, H. Onodera

    Electrical Performance of Electronic Packaging, EPEP   149 - 152   2006

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    Language:English   Publishing type:Research paper (international conference proceedings)  

    DOI: 10.1109/EPEP.2006.321214

  • Low-Power Design of CML Drivers for On-Chip Transmission-Lines Reviewed

    Akira Tsuchiya, Takeshi Kuboki, Hidetoshi Onodera

    SASIMI2006,pp. 177-182   2006

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  • Interconnect RL extraction at a single representative frequency Reviewed

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS   2006   515 - 520   2006

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    Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:IEEE  

    This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. We experimentally verify that the proposed method provides accurate transition waveforms over various interconnect topologies.

    Web of Science

  • Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Reviewed

    T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

    International Workshop on Compact Modeling, pp. 51-56, 2006.   2006

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  • A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection

    Akira Tsuchiya

    2005.11

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    Language:English   Publishing type:Doctoral thesis  

  • A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection Reviewed

    TSUCHIYA Akira

    Kyoto University   2005.11

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    Language:English   Publishing type:Doctoral thesis  

  • CMLを用いたオンチップ長距離高速信号伝送技術の開発

    土谷 亮, 新名 亮規, 橋本 昌宜, 小野寺 秀俊

    第9回システムLSIワークショップ, pp.275--278, Nov 2005.   2005.11

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  • Performance Limitation of On-chip Global Interconnects for High-speed Signaling Reviewed

    A. Tsuchiya, M. Hashimoto, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E88-A ( 4 )   885 - 891   2005.4

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  • Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics Reviewed

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005.   2005

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  • Design guideline for resistive termination of on-chip high-speed interconnects Reviewed

    A. Tsuchiya, M. Hashimoto, H. Onodera

    Proceedings of the Custom Integrated Circuits Conference   2005   608 - 611   2005

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    DOI: 10.1109/CICC.2005.1568742

  • Performance prediction of on-chip high-throughput global signaling Reviewed

    Masanori Hashimoto, Akira Tsuchiya, Akinori Shinmyo, Hidetoshi Onodera

    IEEE Topical Meeting on Electrical Performance of Electronic Packaging   2005   79 - 82   2005

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    On-chip global signaling whose performance improves with technology advance is eagerly demanded. This work focuses on wave pipelining on on-chip transmission lines, which is one of probable solutions, and predicts the trend of signaling performance in the future. Experiments reveal that transmission capacity per channel will improve till at least 35nm technology in 10mm-long or below signaling. We also demonstrate that current-mode differential signaling is robust against power supply noise, but power delivery with non-zero impedance degrades the performance. © 2005 IEEE.

    DOI: 10.1109/EPEP.2005.1563706

    Scopus

  • 配線の伝達特性に基づく抽出周波数決定手法 Reviewed

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    DAシンポジウム 2005, pp.169-174, Aug 2005.   2005

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  • オンチップ高速信号伝送における終端抵抗決定手法 Reviewed

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    第18回 回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005.   2005

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  • Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Reviewed

    A Tsuchiya, M Hashimoto, H Onodera

    SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS   2005   201 - 202   2005

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    This paper discusses shielding effect of power/ground wires in lower layer. A conducting substrate affects characteristics of on-chip transmission line. However in many cases on actual chips, there are P/G wires between the signal wire and the substrate that may shield the substrate coupling. We show measurement and simulation results of on-chip transmission-lines with narrow yet many power/ground wires in a lower layer. Experimental results show that narrow power/ground wires in a lower layer in parallel to the signal wire, which are common in LSI power distribution network, shield substrate coupling and suppress substrate loss. On the other hand, orthogonal power/ground wires in a lower layer hardly mitigate substrate coupling.

    DOI: 10.1109/SPI.2005.1500944

    Web of Science

  • Return path selection for loop RL extraction Reviewed

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2   2   1078 - 1081   2005

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    This paper propose a systematic method to select power/ground wires that should be considered in interconnect R-L extraction. The return current distribution affects loop characteristic of interconnects. To extract exact RL value, all of return paths have to be considered. However it is impossible because there are huge number of P/G wires in LSIs. As more wires are considered, the extraction accuracy improves but the extraction cost increases undesirably. The proposed method focuses the energy dissipated at P/G wires and utilizes it for screening return paths. Experimental results reveal that our method enables accurate and computationally efficient RL extraction with considering return current distribution.

    Web of Science

  • On-chip global signaling by wave pipelining Reviewed

    M Hashimoto, A Tsuchiya, H Onodera

    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING   311 - 314   2004

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    This paper discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.

    Web of Science

  • 配線RL抽出におけるリターンパス選択手法 Reviewed

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    DAシンポジウム 2004, pp.175-180, Jul 2004.   2004

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  • オンチップ伝送線路のリターン電流分布が信号波形に与える影響 — 平衡・不平衡伝送の比較 — Reviewed

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    第17回 回路とシステム軽井沢ワークショップ, pp.567-572, Apr 2004.   2004

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  • Representative frequency for interconnect R(f)L(f)C extraction Reviewed

    A. Tsuchiya, M. Hashimoto, H. Onodera

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC   691 - 696   2004

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  • Performance Prediction of On-chip Global Signaling Reviewed

    M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera

    3rd Electrical Design of Avdanced Packaging and Systems Workshop, pp.87-100, Nov 2004.   2004

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  • Performance limitation of on-chip global interconnects for high-speed signaling Reviewed

    A. Tsuchiya, Y. Gotoh, M. Hashimoto, H. Onodera

    Proceedings of the Custom Integrated Circuits Conference   489 - 492   2004

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  • Representative Frequency for Interconnect R(f)L(f)C Extraction Reviewed

    A. Tsuchiya, M. Hashimoto, H. Onodera

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E86-A ( 12 )   2942 - 2951   2003.12

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  • Representative frequency for interconnect R(f)L(f)C extraction Reviewed

    A Tsuchiya, M Hashimoto, H Onodera

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES   E86A ( 12 )   2942 - 2951   2003.12

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    This paper discusses the frequency to extract RLC values from interconnects. In circuit design, frequency-independent equivalent circuit is widely used, and many design and analysis techniques based on this equivalent circuit are proposed so far. However in reality, characteristics of interconnects are frequency-dependent. Also pulse waveforms in digital circuits contain multiple frequency components. The frequency used for RLC extraction affects the accuracy of interconnect characterization, and hence careful determination of extraction frequency is critical. We propose a representative frequency for RLC extraction. Conventionally, representative frequencies are determined by input pulse. The proposed method decides the representative frequency based on the interconnect length, whereas conventional representative frequencies are determined by input pulse shape, period and patterns. We verify that the extraction at the proposed frequency provides the most accurate transition waveform against various input signals and interconnect structures in digital circuits.

    DOI: 10.1093/ietfec/e88-a.4.885

    Web of Science

  • 周辺配線の影響を考慮したオンチップ高速信号伝送用配線構造

    土谷 亮

    2003.3

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  • 周辺配線の影響を考慮したオンチップ高速信号伝送用配線構造 Reviewed

    土谷 亮

    京都大学   2003.2

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  • Frequency Determination for Interconnect RLC Extraction Reviewed

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2003), pp.288-293, Apr 2003.   2003

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  • 直交配線を持つオンチップ伝送線路の特性評価 Reviewed

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    DA シンポジウム 2003, pp.133-138, Jul 2003.   2003

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  • 配線R(f)L(f)C抽出のための代表周波数決定手法 Reviewed

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    第16回 回路とシステム軽井沢ワークショップ, pp.61-66, Apr 2003.   2003

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  • VLSI 配線の伝送線路特性を考慮した駆動力決定手法 Reviewed

    土谷亮, 橋本昌宜, 小野寺秀俊

    情報処理学会論文誌   43 ( 5 )   1338 - 1347   2002.5

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  • Interconnect Structures for High-Speed Long-Distance Signal Transmission Reviewed

    M. Hashimoto, D. Hiramatsu, A. Tsuchiya, H. Onodera

    15th Annual IEEE International ASIC/SOC Conference, pp. 426--430, Sep 2002.   2002

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  • VLSI配線の伝送線路特性を考慮した駆動力決定手法 Reviewed

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    情報処理学会論文誌   2002

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  • 長距離高速信号伝送を可能にするVLSI配線構造の検討 Reviewed

    平松 大輔, 土谷 亮, 橋本 昌宜, 小野寺 秀俊

    DA シンポジウム 2002, pp.155-160, Jul 2002.   2002

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  • Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects Reviewed

    Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

    10th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2001), pp.377-381, Oct 2001.   2001

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  • VLSI配線の伝送線路化を考慮した駆動力決定手法 Reviewed

    土谷 亮, 小野寺 秀俊

    DA シンポジウム 2001, pp.241-246, Jul 2001.   2001

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Books etc

  • OHM 大学テキスト電気回路II

    竹野裕正 (編著),芳賀宏,廣瀬哲也,土谷亮,久門尚史( Role: Joint author)

    オーム社  2012.10  ( ISBN:978-4274212772

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    Responsible for pages:第9章~第11章   Language:Japanese   Book type:Textbook, survey, introduction

MISC

  • インバータ増幅段によるレギュレーティッドカスコード型トランスインピーダンスアンプの広帯域化

    藤原将倫, 土谷 亮, 中野慎介, 野河正史, 野坂秀之, 小野寺秀俊

    電子情報通信学会技術報告書   IEICE-115 ( 477(ICD) )   229 - 233   2016.3

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    Language:Japanese  

  • インダクティブピーキングを利用したリング型VCOの低ジッタ化に関する研究

    井上 洋, 浜田 泰輔, 岸根 桂路, 中野 慎介, 中村 誠, 土谷 亮, 久保木 猛, 稲葉 博美

    電子情報通信学会総合大会, C-12-65, Mar 2013.   2013.3

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    Language:Japanese  

  • ミリ波帯オンチップ伝送線路における下層シールドの影響

    雨貝太郎, 土谷亮, 中野慎介, 野河正史, 小泉弘, 小野寺秀俊

    電子情報通信学会総合大会, C-12-19, Mar 2013.   2013.3

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    Language:Japanese  

  • トランジスタサイズに着目した微細CMOS D-FF回路の高速化設計手法

    浜田 泰輔, 井上 洋, 岸根 桂路, 土谷 亮, 久保木 猛, 稲葉博美

    電子情報通信学会総合大会, C-12-8, Mar 2013.   2013.3

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    Language:Japanese  

  • レギュレーティッドカスコードを用いた広帯域フィードバック型トランスインピーダンスアンプ

    申 東潤, 土谷 亮, 小野寺秀俊

    2012年電子情報通信学会ソサイエティ大会, C-12-3, Sep 2012   2012.9

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  • インダクティブピーキングを用いた増幅回路における解析的ジッタ予測手法

    榎並達也, 宮脇成和, 土谷亮, 小野寺秀俊, 小野寺秀俊

    電子情報通信学会大会講演論文集   2012   133   2012.3

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    J-GLOBAL

  • 完全差動回路構成GVCOの高速化設計

    川中 啓敬, 岸根 桂路, 土谷 亮, 小野寺 秀俊

    2012年電子情報通信学会総合大会, C-12-46, Mar 2012.   2012.3

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  • 細粒度基板電圧制御に用いるDA変換器

    釡江 典裕, 土谷 亮, 小野寺 秀俊

    2012年電子情報通信学会総合大会, C-12-51, Mar 2012.   2012.3

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  • Effect of Anomalous Skin Effect on Transmission-Line Loss

    TSUCHIYA Akira, ONODERA Hidetoshi

    111 ( 351(MW2011 125-141) )   77 - 81   2011.12

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    Language:Japanese  

    CiNii Books

    J-GLOBAL

  • MOSトランジスタの基板抵抗がインダクティブピーキング回路の周波数特性に与える影響

    宮脇成和, 土谷亮, 小野寺秀俊

    2010年電子情報通信学会ソサイエティ大会, C-12-26, Sep 2010.   2010.9

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  • 基板電圧の制御回路とその面積オーバヘッド

    釡江典裕, 土谷亮, 小野寺秀俊

    2010年電子情報通信学会ソサイエティ大会, C-12-22, Sep 2010.   2010.9

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  • Bandwidth Enhancement for TIA with Mutually Coupled Inductors

    OKUMURA Yoshihiro, NAKAMURA Makoto, KISHINE Keiji, TSUCHIYA Akira, ONODERA Hidetoshi

    IEICE technical report   109 ( 336(ICD2009 76-105) )   157 - 161   2009.12

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    A bandwidth enhancement technique for TransImpedance Amplifier (TIA) is proposed. Bandwidth is an important issue for CMOS high-speed amplifier and inductive peaking is a common practice for bandwidth enhancement. On the other hand, on-chip inductors occupy large area. We propose a inductive peaking with mutually coupled inductors. The mutualy coupled inductors integrates two inductors without area penalty. Experimental results show that the proposed method improves the bandwidth by 9% compared with conventional shunt peaking.

    CiNii Books

    J-GLOBAL

  • オンチップ差動伝送線路の構造と下層配線からのノイズの関係

    久保木猛, 土谷亮, 小野寺秀俊

    電子情報通信学会大会講演論文集   2008   108   2008.9

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    J-GLOBAL

  • Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects

    TSUCHIYA Akira, ONODERA Hidetoshi

    IEICE technical report   107 ( 32 )   55 - 59   2007.5

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    Language:Japanese   Publisher:The Institute of Electronics, Information and Communication Engineers  

    This paper reports measurement results of on-chip interconnects with CMP dummy fill. CMP dummy fill is a floating metal for metal density adjustment. Conventionally, the effect of dummy fill on the interconnect characteristics is discussed mainly from the viewpoint of the capacitance. However in high frequency above 10GHz, the eddy current induced in dummy fills affects the interconnect loss. We fabricated test structures of on-chip interconnect with dummy fills. From the measurement results, the effect of the dummy fills on the wire resistance is not negligible even if the ground wires are adjacent to the signal wire. The dummy fills in the upper/lower metal layer affect the wire resistance and the resistance increases by 20% at 50GHz.

    CiNii Books

  • 将来の微細プロセスにおけるDVSとPower Gatingの比較

    関良平, 土谷亮, 小野寺秀俊

    電子情報通信学会大会講演論文集   2006   56   2006.9

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    J-GLOBAL

  • ロードマップに準拠したSPICEトランジスタモデルの構築

    上村晋一朗, 土谷亮, 橋本昌宜, 小野寺秀俊

    電子情報通信学会大会講演論文集   2006   81   2006.3

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    J-GLOBAL

  • 配線とトランジスタのばらつきを考慮したバッファの挿入方法

    福岡孝之, 土谷亮, 小野寺秀俊

    電子情報通信学会大会講演論文集   2006   77   2006.3

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    J-GLOBAL

  • オンチップ伝送線路の基板損失に対する下層配線の影響

    土谷亮, 橋本昌宜, 小野寺秀俊

    電子情報通信学会大会講演論文集   2005   77   2005.3

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    J-GLOBAL

  • オンチップ高速信号伝送用線路の解析的性能評価

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    信学技報, vol. 104, No. 709, pp. 49-54, Mar 2005.   2005.3

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    Language:Japanese  

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Industrial property rights

  • Inductor

    Yusuke Otomo, Hiroaki Katsurai, Hidetoshi Onodera, Akira Tsuchiya

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    Application no:特願PCT/JP2011/070993  Date applied:2011.9

    Publication no:特表WO/2012/036207  Date published:2012.3

    Patent/Registration no:特許5463580 

  • ソレノイドインダクタ

    中村 誠,小野寺 秀俊,土谷 亮

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    Announcement no:特開2014-22484  Date announced:2014.2

    Country of applicant:Domestic  

  • 可変インダクタおよびトランスインピーダンスアンプ

    中村 誠,小野寺 秀俊,土谷 亮

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    Announcement no:特開2013-251589  Date announced:2013.12

    Country of applicant:Domestic  

  • トランスインピーダンスアンプ

    中村 誠,小野寺 秀俊,土谷 亮

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    Announcement no:特開2013-247423  Date announced:2013.12

    Country of applicant:Domestic  

  • トランスインピーダンスアンプ

    中村 誠,小野寺 秀俊,土谷 亮

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    Announcement no:特開2012-257070  Date announced:2012.12

    Country of applicant:Domestic  

  • 高周波伝送線路

    中野 慎介,野河 正史,小泉 弘,土谷 亮,小野寺 秀俊,雨貝 太郎

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    Announcement no:特開2014-220727  Date announced:2014.11

    Country of applicant:Domestic  

  • Inductor

    大友 祐輔,桂井 宏明,小野寺 秀俊,土谷 亮

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    Patent/Registration no:CN103168354 B  Date registered:2015.11  Date issued:2015.11

    Country of applicant:Foreign country  

  • Inductor

    大友 祐輔,桂井 宏明,小野寺 秀俊,土谷 亮

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    Patent/Registration no:US9082543 B2  Date registered:2015.7  Date issued:2015.7

    Country of applicant:Foreign country  

  • インダクタ (Inductor)

    大友 祐輔,桂井 宏明,小野寺 秀俊,土谷 亮

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    Patent/Registration no:WO2012036207 A1  Date registered:2012.3  Date issued:2012.3

    Country of applicant:Foreign country  

  • トランスインピーダンスアンプ

    中村 誠,小野寺 秀俊,土谷 亮

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    Patent/Registration no:第5137141号  Date registered:2012.11  Date issued:2012.11

    Country of applicant:Domestic  

  • トランスインピーダンスアンプ

    中村 誠,岸根 桂路,小野寺 秀俊,土谷 亮

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    Patent/Registration no:第5147061号  Date registered:2012.12  Date issued:2012.12

    Country of applicant:Domestic  

  • 直交型ソレノイドインダクタ

    中野 慎介,野河 正史,雨貝 太郎,土谷 亮,小野寺 秀俊

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    Application no:2014-086117 

    Announcement no:特開2015-207614  Date announced:2015.11

    Patent/Registration no:6327639  Date registered:2017.4  Date issued:2017.4

    Country of applicant:Domestic  

  • ソレノイドインダクタ

    中野 慎介,野河 正史,雨貝 太郎,土谷 亮,小野寺 秀俊

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    Application no:2014-086116 

    Announcement no:特開2015-207613  Date announced:2015.11

    Patent/Registration no:6327638  Date registered:2017.4  Date issued:2017.4

    Country of applicant:Domestic  

  • 出力回路および送受信回路

    中村 誠,小野寺 秀俊,土谷 亮

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    Announcement no:特開2015-19134  Date announced:2015.1

    Country of applicant:Domestic  

  • 低損失伝送線路

    中野 慎介,野河 正史,小泉 弘,土谷 亮,小野寺 秀俊

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    Announcement no:特開2014-230184  Date announced:2014.12

    Country of applicant:Domestic  

  • 高周波伝送線路

    中野 慎介, 野河 正史, 小泉 弘, 土谷 亮, 小野寺 秀俊, 雨貝 太郎

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    Application no:特願2013-099883 

    Announcement no:特開2014-220727 

  • 可変インダクタおよびトランスインピーダンスアンプ

    中村 誠, 小野寺 秀俊, 土谷 亮

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    Application no:特願2012-122702 

    Announcement no:特開2013-251589 

  • 出力回路および送受信回路

    中村 誠, 小野寺 秀俊, 土谷 亮

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    Application no:特願2013-143254 

    Announcement no:特開2015-019134 

  • 低損失伝送線路

    中野 慎介, 野河 正史, 小泉 弘, 土谷 亮, 小野寺 秀俊

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    Application no:特願2013-109602 

    Announcement no:特開2014-230184 

  • トランスインピーダンスアンプ

    中村 誠, 岸根 桂路, 小野寺 秀俊, 土谷 亮

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    Announcement no:特開2010-16740  Date announced:2010.1

    Patent/Registration no:特許5147061 

  • トランスインピーダンスアンプ

    中村 誠, 小野寺 秀俊, 土谷 亮

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    Application no:特願2011-128884 

    Announcement no:特開2012-257070 

  • トランスインピーダンスアンプ

    中村 誠, 小野寺 秀俊, 土谷 亮, 宮脇 成和

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    Application no:特願2012-118264 

    Announcement no:特開2013-247423 

  • トランスインピーダンスアンプ

    中村 誠, 小野寺 秀俊, 土谷 亮

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    Application no:特願2009-172791 

    Announcement no:特開2011-029872 

    Patent/Registration no:特許5137141 

  • ソレノイドインダクタ

    中村 誠, 小野寺 秀俊, 土谷 亮

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    Application no:特願2012-158359 

    Announcement no:特開2014-022484 

  • インダクタ

    大友 祐輔, 桂井 宏明, 小野寺 秀俊, 土谷 亮

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    Application no:特願2012-534037 

    Patent/Registration no:特許5463580 

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Awards

  • 編集活動感謝状

    2024.9   電子情報通信学会 基礎・境界ソサイエティ  

    土谷 亮

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    Award type:Honored in official journal of a scientific society, scientific journal 

    査読委員としての貢献

  • DAシンポジウム2022 セッション特別賞

    2023.8   情報処理学会 システムとLSIの設計技術研究会   線形分類器による探索領域の刈り込みがアナログ回路のパラメータ最適化に与える影響

    山下 太一,阿南 椋久,土谷 亮,井上 敏之,岸根 桂路

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    Award type:Award from Japanese society, conference, symposium, etc. 

  • DAシンポジウム2022 セッション特別賞

    2023.8   情報処理学会 システムとLSIの設計技術研究会   オープンソースのアナログ回路自動設計に向けたブロック方式設計のSkywater130nmプロセスによる実証

    阿南 椋久,山下 太一,土谷 亮,井上 敏之,岸根 桂路

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    Award type:Award from Japanese society, conference, symposium, etc. 

  • デザインガイア2022 優秀ポスター賞

    2022.11   情報処理学会   大きさの異なる2つのコプレーナ型静電容量センサを用いた液滴の接触角推定手法

    古田 翼,土谷 亮,井上 敏之,岸根 桂路

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 情報処理学会 SLDM研究会 セッション特別賞

    2022.8   情報処理学会   増幅回路のパラメータ最適化における性能指標の事前予測による探索時間短縮

    山下 太一,土谷 亮,井上 敏之,岸根 桂路

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • IEEE CEDA All Japan Joint Chapter SASIMI Young Researcher Award

    2021.3   The 23rd Workshop on Synthesis And System Integration of Mixed Information Technologies   A Transimpedance Amplifier Topology Considering the Impact of Variability on Inductive Peaking

    Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

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    Award type:Award from international society, conference, symposium, etc.  Country:Japan

  • ELEX Editorial Contribution Award

    2020.6   IEICE Electronics Express  

    Akira Tsuchiya

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    Country:Japan

  • ISOCC 2019 ZINITIX Award

    2019.10   ISOCC 2019   Suitable-Compensation Circuit Design for a PAM4 transmitter in 180-nm CMOS

    Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

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    Award type:Award from international society, conference, symposium, etc.  Country:Korea, Republic of

  • ISOCC 2019 IEEE SSCS Seoul Chapter Award

    2019.10   IEEE SSCS Seoul Chapter   Frequency Discriminator Using a Simple AD Converter for Interface Systems

    Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

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    Award type:Award from international society, conference, symposium, etc.  Country:Korea, Republic of

  • システムと信号処理サブソサイエティ 貢献賞

    2017.5   電子情報通信学会  

    土谷 亮

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    Country:Japan

  • 電子情報通信学会 エレクトロニクスソサイエティ 功労表彰

    2017.3   電子情報通信学会   集積回路研究専門委員会 幹事補佐としての貢献

    土谷 亮

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • VDEC デザインアワード敢闘賞

    2013.8   東京大学大規模集積システム設計教育研究センター   セルベース回路と混載可能な基板バイアス電圧生成回路

    釡江 典裕

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 情報処理学会 SLDM 研究会 優秀発表学生賞

    2013.8   情報処理学会 SLDM研究会   Analysis of Radiation-Induced Timing Vulnerability on Phase-locked Loops

    金 信寧

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • RASEDA-10 “Jury’s Special Award”

    2012.12   10th International Workshop on Radiation Eects on Semiconductor Devices for Space Applications   Dual-PLL based on Temporal Redundancy for Radiation-Hardening

    金 信寧

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    Award type:Award from international society, conference, symposium, etc.  Country:Japan

  • IEEE 関西支部学生研究奨励賞

    2011.12   IEEE Kansai Chapter   Variation-sensitive monitor circuits for estimation of Die-to-Die process variation

    A.K.M. Mahfuzul Islam

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • IEEE 関西支部学生研究奨励賞

    2011.12   IEEE Kansai Chapter   A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18um CMOS

    久保木 猛

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • International SoC Design Conference Samsung Award

    2011.11   International SoC Design Conference   A 10.3Gbps TransImpedance Amplifier with Mutually Coupled Inductors in 0.18-um CMOS

    Shigekazu Miyawaki

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    Award type:Award from international society, conference, symposium, etc.  Country:Korea, Republic of

  • 情報処理学会 SLDM 研究会 優秀発表学生賞

    2010.9   情報処理学会 SLDM研究会   チップ内ばらつきが順序セルの動作特性に与える影響

    砂川 洋輝

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 情報処理学会 SLDM 研究会 優秀発表学生賞

    2008.8   情報処理学会 SLDM研究会   統計的遅延解析における遅延分布間の最大値計算手法

    寺田 晴彦

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 第 20 回 回路とシステム軽井沢ワークショップ 奨励賞

    2008.4   回路とシステムワークショップ実行委員会   ダミーフィルがオンチップ配線の高周波特性に与える影響の解析的評価手法

    土谷 亮

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 第 23 回 井上研究奨励賞

    2007.2   井上科学振興財団   LSI 内高性能配線のモデル化および設計手法に関する研究

    土谷 亮

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • Karuizawa Workshop IEEE CAS Japan Chapter Student Paper Award

    2006.4   IEEE CAS Japan Chapter   オンチップ高速信号伝送における終端抵抗決定手法

    土谷 亮

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 平成 17 年度 電子情報通信学会 学術奨励賞

    2006.3   電子情報通信学会   オンチップ伝送線路の基板損失に対する下層配線の影響

    土谷 亮

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 平成 17 年度 (第 29 回) 丹羽保次郎記念論文賞

    2006.1   東京電機大学   Representative Frequency for Interconnect R(f)L(f)C Extraction

    土谷 亮

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • ASP-DAC2004 Best Paper Award

    2004.1   Asia and South Pacific Design Automation Conference   Representative Frequency for Interconnect R(f)L(f)C Extraction

    Akira Tsuchiya

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    Award type:Award from international society, conference, symposium, etc.  Country:Japan

  • 平成 14 年 情報処理学会 SLDM 研究会 優秀論文賞

    2002.7   情報処理学会 SLDM研究会   VLSI 配線の伝送線路化を考慮した駆動力決定手法

    土谷 亮

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

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Research Projects

  • レイアウトジェネレータの研究

    2023.7 - 2024.6

    株式会社ロジック・リサーチ 

  • マイクロ流路デバイスの高度化に向けた平面型液体接触角センサの開発

    2023.4 - 2026.3

    日本学術振興会  科学研究費補助金 (基盤研究(C)) 

    土谷 亮

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    Grant amount:\2800000 ( Direct Cost: \2800000 )

  • スケーラビリティを実現するRFフロントエンド回路技術の開発

    2022.10 - 2024.3

    科学技術振興機構  ムーンショット型研究開発事業  受託研究

    土谷 亮

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    Grant amount:\72800000 ( Direct Cost: \72800000 )

    ムーンショット型研究開発事業 目標6「2050年までに、経済・産業・安全保障を飛躍的に発展させる誤り耐性型汎用量子コンピュータを実現」
    「スケーラブルな高集積量子誤り訂正システムの開発」(小林和淑PM)
    研究開発項目4

  • Beyond 5G超大容量無線通信を支える次世代エッジクラウドコンピュ ―ティング基盤の研究開発

    2021.3 - 2023.3

    情報通信研究機構  受託研究

    岸根桂路

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    Grant amount:\81990040 ( Direct Cost: \81990040 )

  • 多並列光受信回路におけるクロストーク低減技術の研究

    2016.5 - 2017.3

    NTT先端集積デバイス研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • 多様な光・電気融合システムに対応可能な高速・低電力・小面積光受信回路の設計手法

    2016.4 - 2019.3

    科学研究費補助金(若手(B)) 

    土谷 亮

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    Grant amount:\4160000 ( Direct Cost: \3120000 、 Indirect Cost:\1040000 )

  • 小型帯域延伸回路を活用した光受信フロントエンドの低電力・広帯域化設計技術の研究

    2015.9 - 2016.3

    NTT先端集積デバイス研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • SI-PH 集積化へ向けた高密度受動素子による超高速 CMOS-IF の小型化設計技術の研究

    2014.5 - 2015.3

    NTT先端集積デバイス研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • Si-PH 集積化に向けた高周波回路の小型化設計技術の研究

    2013.5 - 2014.3

    NTT マイクロシステムインテグレーション研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • 通信用 SoC に向けた超広帯域 CMOS 回路設計技術の研究

    2012.5 - 2013.3

    NTT マイクロシステムインテグレーション研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • 誘導性結合インダクタを用いた CMOS 光/電気インターフェース回路の研究

    2011.5 - 2013.3

    NTTフォトニクス研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • CMOS 光/電気インターフェース回路の研究

    2010.5 - 2011.3

    NTTフォトニクス研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • 光通信用超高速ドライバの動作実験

    2010.5 - 2011.3

    NTT マイクロシステムインテグレーション研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • 高密度インダクタを用いた高速 LD ドライバの研究

    2009.5 - 2010.3

    NTT マイクロシステムインテグレーション研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • チップ内メタ物質を用いたミリ波集積回路用小型・可変伝送線路共振器の開発

    2009.4 - 2011.3

    科学研究費補助金 (若手(B)) 

    土谷 亮

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    Grant amount:\4290000 ( Direct Cost: \3210000 、 Indirect Cost:\1080000 )

  • 高速 CMOS ドライバ回路の研究

    2008.5 - 2009.3

    NTT マイクロシステムインテグレーション研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • フローティングメタルを用いたオンチップ伝送線路の特性制御技術に関する研究

    2008.4 - 2009.3

    京都大学グローバルCOE若手グラント  その他のプロジェクト

    土谷 亮

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    Grant amount:\1000000 ( Direct Cost: \1000000 )

  • 高速 CMOS アナログ回路の研究

    2007.5 - 2009.3

    NTTフォトニクス研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • 寄生インダクタを考慮した高速回路の研究

    2007.5 - 2008.3

    NTT マイクロシステムインテグレーション研究所  共同研究

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    Grant amount:\3000000 ( Direct Cost: \2400000 、 Indirect Cost:\600000 )

  • CMOS optical transmitter and receiver

    2007.4

    Cooperative Research  CMOS, laser-diode driver, transimpedance amplifier, inductive peaking

  • 特別研究員奨励費

    2004.4 - 2005.11

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    Grant amount:\2000000 ( Direct Cost: \2000000 )

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Presentations

  • オンチップ配線を用いた静電容量式コプレーナ型接触角センサ

    福井快肇,土谷亮,井上敏之,岸根桂路

    デザインガイア2024  2024.11  電子情報通信学会・情報処理学会

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    Event date: 2024.11

    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:コンパルホール  

  • 日本におけるオープンソースシリコンコミュニティの立ち上げと活動の1 年 Invited

    今村 謙之,土谷 亮,久保木 猛,森 瑞紀

    デザインガイア2024  2024.11  電子情報通信学会・情報処理学会

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    Event date: 2024.11

    Language:Japanese   Presentation type:Oral presentation (invited, special)  

    Venue:コンパルホール  

  • 極低温状態での集積回路内配線におけるサイズ効果が遅延時間に与える影響

    植田達矢,土谷亮,井上敏之,岸根桂路

    デザインガイア2024  2024.11  電子情報通信学会・情報処理学会

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    Event date: 2024.11

    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:コンパルホール  

  • 研究会の楽しみ方 Invited

    土谷 亮

    IEICE ICD/CAS 学生・若手研究会  2023.12  電子情報通信学会

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    Event date: 2023.12

    Language:Japanese   Presentation type:Oral presentation (invited, special)  

    Venue:アマホームPLAZA  

  • 極低温状態での集積回路内配線における異常表皮効果のモデル化

    植田達矢,土谷亮,井上敏之,岸根桂路

    IEICE ICD/CAS 学生・若手研究会  2023.12  電子情報通信学会

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    Event date: 2023.12

    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:アマホームPLAZA  

  • 極低温におけるアナログ回路のMOSサイズと動作可能範囲の関係

    北村 昂史,土谷 亮, 岸根 桂路, 井上 敏之

    IEICE ICD/CAS 学生・若手研究会  2023.12  電子情報通信学会

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    Event date: 2023.12

    Language:Japanese   Presentation type:Poster presentation  

    Venue:アマホームPLAZA  

  • 静電容量式コプレーナ型接触角推定センサの液滴端位置依存性

    福井 快肇,土谷 亮,岸根 桂路,井上 敏之

    IEICE ICD/CAS 学生・若手研究会  2023.12  電子情報通信学会

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    Event date: 2023.12

    Language:Japanese   Presentation type:Poster presentation  

    Venue:アマホームPLAZA  

  • Contact angle estimation using coplanar capacitors considering non non-orthogonal state of droplet edge and electrodes

    2023.11 

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    Event date: 2023.11

    Language:Japanese   Presentation type:Poster presentation  

  • 超々小型衛星フォーメーションフライト用高集積度通信機器とopen source PDK の利用

    今村 謙之, 土谷 亮, 森岡 澄夫, 野田 篤司, 片野 将太郎

    第67回宇宙科学技術連合講演会  2023.10  日本航空宇宙学会

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    Event date: 2023.10

    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:富山国際会議場  

  • 超々小型衛星用ASICのプロトタイピングにおけるOpenMPW活用の有効性検討

    今村 謙之,土谷 亮,森岡 澄夫,野田 篤司,片野 将太郎

    DAシンポジウム 2023  2023.8  情報処理学会

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    Event date: 2023.8 - 2023.9

    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:加賀  

  • アナログ回路の設計難易度の数値化による性能要件評価

    阿南 椋久,土谷 亮,岸根 桂路,井上 敏之

    DAシンポジウム 2023  2023.8  情報処理学会

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    Event date: 2023.8 - 2023.9

    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:加賀  

  • オープンに利用可能な製造プロセスのトランジスタ特性とアナログ回路性能の比較

    土谷 亮

    LSIとシステムのワークショップ2023  2023.5  電子情報通信学会 集積回路研究専門委員会

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    Language:Japanese   Presentation type:Poster presentation  

    Venue:東京大学  

  • Design Automation of Analog Circuits for Open-Source Integrated Ci Invited

    2023.3 

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  • LSI民主化時代の国内コミュニティはどうあるべきか Invited

    土谷 亮

    ICD 学生・若手研究会  2023.3  電子情報通信学会

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    Language:Japanese   Presentation type:Symposium, workshop panel (nominated)  

    Venue:日光市藤原公民館  

  • 大きさの異なる2つのコプレーナ型静電容量センサを用いた液滴の接触角推定手法

    古田 翼,土谷 亮,井上 敏之,岸根 桂路

    デザインガイア2022  2022.11  電子情報通信学会,情報処理学会

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    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:金沢市文化ホール  

  • Flat-Shape Capacitive Sensor of Droplet Contact-Angle for Electrowetting-on-Dielectric Microfluidic Systems International conference

    Tomohiro Kodaniguchi, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

    24th Workshop on Synthesis And System Integration of Mixed Information Technologies  2022.10  SASIMI 2022 Organizaing Committee

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    Language:English   Presentation type:Poster presentation  

    Venue:Hirosaki  

  • シングルチャネル/マルチポート制御システムにおける同符号連続パターン埋込による制御情報付加手法

    種 龍之介,中塩屋真也,井上敏之,土谷 亮,岸根桂路

    電子情報通信学会 2022年ソサイエティ大会  2022.9  電子情報通信学会

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    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:オンライン  

  • 線形分類器による探索領域の刈り込みが アナログ回路のパラメータ最適化に与える影響

    山下太一,阿南椋久,土谷亮,井上敏之,岸根桂路

    DAシンポジウム2022  2022.8  情報処理学会

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    Language:Japanese   Presentation type:Oral presentation (general)  

    Venue:鳥羽シーサイドホテル  

  • オープンソースのアナログ回路自動設計に向けたブロック方式設計のSkywater 130nmプロセスによる実証

    阿南椋久,山下太一,土谷亮,井上敏之,岸根桂路

    DAシンポジウム2022  2022.8  情報処理学会

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    Venue:鳥羽シーサイドホテル  

  • 演算リソースの効率的分散運用に向けたFPGA SoCシステム設計

    寺村優希, 山崎怜, 畑野響, 井上敏之, 土谷亮, 岸根桂路

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • PAM4 伝送システムへの周波数変調技術適応の検討

    中塩屋真也, 宮部雅也, 井上敏之, 土谷亮, 岸根桂路

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • 25-Gb/s出力インピーダンス可変レーザドライバ回路

    井上敏之, 土谷亮, 岸根桂路, 伊藤大輔, 高橋康宏, 中村 誠

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • オンチップバイアス Tを用いた光パケット通信用バーストモードドライバ回路

    伊藤大輔, 高橋康宏, 中村誠, 井上敏之, 土谷亮, 岸根桂路

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • 局部帰還を有する多段RGC-TIA回路の一設計

    高橋康宏, 伊藤大輔, 中村誠, 土谷亮, 井上敏之, 岸根桂路

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • 24-GHz帯マイクロ波センサのビームフォーミングに向けたアナログ移相量制御方式の検討

    井上正隆, 井上敏之, 土谷亮, 岸根桂路

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • 複数人対応見守りシステムに向けたFPGA深層学習推論処理におけるハードウェアリソース使用量削減手法

    岡本真尚, 井上敏之, 土谷亮, 岸根桂路

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • 伝送線路で接続された光通信用トランスインピーダンスアンプの入力インピーダンスが波形に与える影響

    土谷亮, 井上敏之, 高橋康宏, 伊藤大輔, 岸根桂路, 中村 誠

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • 三結合インダクタによって生じる結合係数の設計範囲拡大を目的とした構造の検討

    浅岡知哉, 土谷 亮, 土田知史, 岸根桂路, 井上敏之

    2022年電子情報通信学会総合大会  2022.3  電子情報通信学会

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    Venue:オンライン  

  • 増幅回路のパラメータ最適化における性能指標の事前予測による探索時間短縮

    山下太一,土谷亮,井上敏之,岸根桂路

    DAシンポジウム2021  2021.9  情報処理学会

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    Venue:オンライン  

  • 低電力・低電源ノイズを両立する多段構成トランスインピーダンスアンプの設計手法

    中田 吉弥,土谷 亮,井上 敏之,岸根 桂路

    LSIとシステムのワークショップ  2021.5  電子情報通信学会

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    Venue:オンライン  

  • A Transimpedance Amplifier Topology Considering the Impact of Variability on Inductive Peaking International conference

    Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

    The 23rd Workshop on Synthesis And System Integration of Mixed Information Technologies  2021.3 

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    Venue:Online  

  • オフセット制御機能付きプリアンプを用いたPAM4 レシーバの出力性能向上に向けた検討

    宮部雅也,井上敏之,土谷 亮,岸根桂路

    電子情報通信学会 総合大会  2021.3  電子情報通信学会

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  • 静電容量を利用した液滴の接触角推定における対応範囲拡大の検討

    小谷口朋大,土谷 亮,井上敏之,岸根桂路

    デザインガイア2020  2020.11  電子情報通信学会

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    Venue:オンライン  

  • シングルチャネルマルチポート制御システムにおける送受信回路デジタル化の検討

    今城篤人,井上敏之,木村山紫郎,西口健太,土谷 亮,岸根桂路

    電子情報通信学会 総合大会  2020.3  電子情報通信学会

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  • 非接触心拍計測システムおけるディジタルフィルタ回路規模削減手法の検討

    吉村侑恭,井上敏之,土谷 亮,岸根桂路

    電子情報通信学会 総合大会  2020.3  電子情報通信学会

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  • ブロック方式におけるモデル化誤差を考慮した配線ブロック数と面積の関係

    岩田智成,土谷 亮,谷村信哉,井上俊之,岸根桂路

    電子情報通信学会 総合大会  2020.3  電子情報通信学会

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  • RGC-TIAにおける多層インダクタによる面積効率向上効果の評価

    田中大夢,土谷 亮,谷村信哉,井上敏之,岸根桂路

    電子情報通信学会 総合大会  2020.3  電子情報通信学会

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  • センサーノードにおける太陽光発電の発電量予測手法の検討

    土谷 亮

    デザインガイア2019  2019.11  電子情報通信学会,情報処理学会

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    Venue:愛媛県男女共同参画センター  

  • RGC-TIAの利得が帯域と入力換算雑音の関係に与える影響

    中田吉弥,土谷 亮,谷村信哉,井上敏之,岸根桂路

    2019年電子情報通信学会ソサイエティ大会  2019.9  電子情報通信学会

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    Venue:大阪大学豊中キャンパス  

  • マイクロ波センサ直交信号を用いたFPGAによるデータ取得時間短縮手法の検討

    吉村侑恭,西口健太,井上敏之,土谷 亮,岸根桂路

    電子情報通信学会総合大会  2019.3  電子情報通信学会

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    Venue:早稲田大学  

  • 多チャンネル実装トランスインピーダンスアンプにおける電源ノイズ削減フィルタの設計手法

    谷村信哉,土谷 亮,野口凌輔,井上敏之,岸根桂路

    電子情報通信学会総合大会  2019.3  電子情報通信学会

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    Venue:早稲田大学  

  • シングルチャネルシステム実現に向けた周波数識別回路の検討

    今城篤人,野口凌輔,井上敏之,土谷 亮,岸根桂路

    電子情報通信学会総合大会  2019.3  電子情報通信学会

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    Venue:早稲田大学  

  • キャリア周波数識別の高分解能化を目指したディスチャージ遅延回路の検討

    木村山紫郎,井上敏之,野口凌輔,土谷亮,岸根桂路

    電気関係学会関西連合大会  2018.12  電気関係学会

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    Venue:大阪  

  • 脈拍センサを用いた呼吸統制下における自律神経状態推定システムの検討

    牧将平,井上敏之,土谷亮,岸根桂路

    電気関係学会関西連合大会  2018.12  電気関係学会

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    Venue:大阪  

  • 入出力インタフェースを実装したFPGAリアルタイム画像処理システムの構築

    西口健太, 井上敏之, 小郷原一智, 土谷 亮, 岸根桂路

    電子情報通信学会ソサイエティ大会  2018.9  電子情報通信学会

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    Venue:金沢大学  

  • ウェアラブルセンサと簡易無線モジュールによる筋疲労計測システムの検討

    水野佑哉, 牧 将平, 荒内航貴, 井上敏之, 土谷 亮, 岸根桂路

    電子情報通信学会 総合大会  2018.3  電子情報通信学会

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    Venue:東京電機大学  

  • 100-Gb/s低電力光通信トランシーバ用CML-CMOSレベル変換回路の検討

    野口凌輔, 香田夏幸, 野村幸平, 土谷 亮, 井上敏之, 岸根桂路

    電子情報通信学会 総合大会  2018.3  電子情報通信学会

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    Venue:東京電機大学  

  • XBeeと脈波センサを用いた自律神経機能検知システムの検討

    牧 将平,荒内航貴,水野佑哉,井上敏之,土谷 亮,岸根桂路

    電気学会 電子回路研究会  2018.3  電気学会

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    Venue:日立製作所 研究開発グループ 生産イノベーションセンタ  

  • 野外における2.4Ghz帯無線モジュールの通信可能距離の実測評価

    高杉陽介, 土谷 亮, 井上敏之, 岸根桂路

    電子情報通信学会 集積回路研究会  2018.3  電子情報通信学会

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    Language:Japanese   Presentation type:Poster presentation  

    Venue:滋賀県立大学  

  • チップ内多層インダクタの構造と特性の関係評価

    土谷 亮

    電子情報通信学会 集積回路研究会  2018.3  電子情報通信学会

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    Venue:滋賀県立大学  

  • 高密度・高速光インターコネクトに向けたCMOS光受信回路の開発 Invited

    土谷 亮,中尾 拓矢,中野慎介,野河正史,野坂秀之,小野寺秀俊

    電子情報通信学会 回路とシステム研究会  2017.2 

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  • インバータ増幅段によるレギュレーティッドカスコード型トランスインピーダンスアンプの広帯域化

    藤原将倫,土谷 亮,中野慎介,野河正史,野坂秀之,小野寺秀俊

    電子情報通信学会集積回路研究専門委員会  2016.3 

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  • A 32-Gb/s output buffer circuit with doubled pre-emphasis in 65-nm CMOS International conference

    T. Tanaka, K. Kishine, D. Omoto, A. Tsuchiya, H. Inaba

    International Conference on Electronics, Information, and Communication  2016.1 

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  • Impact of Anomalous Skin Effect on Metal Wire for Terahertz Integrated Circuit Invited International conference

    Akira Tsuchiya, Hidetoshi Onodera

    IEEE International Symposium on Radio-Frequency Integration Technology  2015.8 

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  • Design of Multi-Layered On-Chip Inductor for Inductive Peaking Invited International conference

    Akira Tsuchiya, Hidetoshi Onodera

    Vietnum-Japan MicroWave 2015  2015.8 

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  • Design of Multi-Layered On-Chip Inductor for Inductive Peaking Invited International conference

    A. Tsuchiya, H. Onodera

    Vietnum-Japam MicroWave  2015.8 

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  • Impact of Anomalous Skin Effect on Metal Wire for Terahertz Integrated Circuit Invited International conference

    A. Tsuchiya, H. Onodera

    IEEE International Symposium on Radio-Frequency Integration Technology  2015.8 

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    Language:English   Presentation type:Oral presentation (invited, special)  

  • インバータ型アンプのためのピーキング手法の検討

    中尾 拓矢, 土谷 亮, 小野寺 秀俊

    第40回アナログRF研究会  2015.6 

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  • 異常表皮効果の材料・温度依存性

    土谷 亮, 小野寺 秀俊

    第40回アナログRF研究会  2015.6 

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  • 集積回路配線によるテラヘルツ帯メタ表面の構成に関する検討

    土谷 亮, 小野寺 秀俊

    第38回アナログRF研究会  2015.3 

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  • Energy reduction by built-in body biasing with single supply voltage operation International conference

    N. Kamae, A.K.M. Mahfuzul Islam, A. Tsuchiya, H. Onodera

    International Symposium on Quality Electronic Devices  2015.3 

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  • SKILL言語による光通信用高速アンプのレイアウト自動生成に関する検討

    土谷 亮, 盛 健次, 小野寺 秀俊

    第37回アナログRF研究会  2014.12 

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  • On-Chip Coupled Inductor for Area-Efficient Inductive Peaking Invited International conference

    Akira Tsuchiya, Taro Amagai, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera

    Thailand-Japan Microwave  2014.11 

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  • On-Chip Coupled Inductor for Area-Efficient Inductive Peaking Invited International conference

    A. Tsuchiya, T. Amagai, S. Nakano, M. Nogawa, H. Koizumi, H. Onodera

    Thailand-Japan MicroWave  2014.11 

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  • A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation International conference

    N. Kamae, A.K.M. Mahfuzul Islam, A. Tsuchiya, H. Onodera

    IEEE Asian SolidState Circuits Conference  2014.11 

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  • 25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS International conference

    T. Tanaka, K. Kishine, H. Inaba, A. Tsuchiya

    International SoC Design Conference  2014.11 

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  • PLL の物理レイアウト自動生成を目指した設計手法

    釡江 典裕, 土谷 亮, 石原 亨, 小野寺 秀俊

    DA シンポジウム 2014   2014.8 

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  • A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops International conference

    K. Kishine, H. Inoue, H. Inaba, M. Nakamura, A. Tsuchiya, H. Onodera, H. Katsurai

    IEEE International Symposium on Circuits and Systems  2014.6 

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  • 電磁界解析における異常表皮効果の扱いに関する考察

    土谷 亮, 小野寺 秀俊

    第35回アナログRF研究会  2014.3 

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  • Analysis of Radiation-Induced Timing Vulnerability on Phaselocked Loops

    S.N. Kim, A. Tsuchiya, H. Onodera

    DA シンポジウム 2013   2013.8 

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  • Perturbation-immune radiation-hardened PLL with a switchable DMR structure International conference

    S.N. Kim, A. Tsuchiya, H. Onodera

    IEEE 19th International On-Line Testing Symposium  2013.7 

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  • Modeling Issues of On-Chip Transmission-Line for Terahertz Integrated Circuit Invited International conference

    A. Tsuchiya, H. Onodera

    Collaborative Conference on Materials Research  2013.6 

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  • Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits International conference

    A. Tsuchiya, H. Onodera

    International Meeting for Future of Electron Devices, Kansai  2013.6 

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  • Modeling Issues of On-Chip Transmission-Line for Terahertz Integrated Circuit Invited International conference

    Collaborative Conference on Materials Research 2013  2013.6 

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  • A slow-wave transmission line with thin pillars for millimeter-wave CMOS International conference

    T. Amagai, A. Tsuchiya, S. Nakano, M. Nogawa, H. Koizumi, H. Onodera

    17th IEEE Workshop on Signal and Power Integrity  2013.5 

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  • ミリ波帯オンチップ伝送線路における下層シールドの影響

    雨貝太郎,土谷 亮,中野慎介,野河正史,小泉弘,小野寺秀俊

    電子情報通信学会総合大会  2013.3 

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  • テラヘルツ集積回路に向けたオンチップ伝送線路のモデル化に関する考察

    土谷 亮,小野寺 秀俊

    電子情報通信学会マイクロ波研究会  2013.3 

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  • インダクティブピー キングを利用したリング型 VCO の低ジッタ化に関する研究

    井上 洋, 浜田 泰輔, 岸根 桂路, 中野 慎介, 中村 誠, 土谷 亮, 久保木 猛, 稲葉 博美

    電子情報通信学会総合大会  2013.3 

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  • トランジスタサイズに着目した微細 CMOS D-FF 回路の高速化設計手法

    浜田 泰輔, 井上 洋, 岸根 桂路, 土谷 亮, 久保木 猛, 稲葉博美

    電子情報通信学会総合大会  2013.3 

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  • テラヘルツ集積回路に向けたオンチップ伝送線路のモデル化に関する考察 Invited

    土谷 亮, 小野寺 秀俊

    電子情報通信学会マイクロ波研究会  2013.3  電子情報通信学会

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  • A 25-Gb/s LD driver with area effective inductor in a 0.18-µm CMOS International conference

    T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

    Asia and South Pacific Design Automation Conference  2013.1 

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  • Dual-PLL based on Temporal Redundancy for Radiation Hardening International conference

    S.N. Kim, A. Tsuchiya, H. Onodera

    10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications  2012.12 

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  • 3次元電磁界解析におけるビアのモデル化方法の考察

    土谷 亮, 小野寺 秀俊

    第31回 シリコンアナログRF研究会, Dec 2012.  2012.12 

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  • A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation International conference

    N. Kamae, A. Tsuchiya, H. Onodera

    IEEE Asian Solid-State Circuits Conference  2012.11 

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  • Modeling of Single-Event Failures in Dividerand PFD of PLLs based on Jitter Analysis International conference

    S.N. Kim, A. Tsuchiya, H. Onodera

    13th European Conference on Radiation and Its Effects on Components and Systems  2012.9 

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  • レギュレーティッドカスコードを用いた広帯域フィードバック型トラ ンスインピーダンスアンプ

    申 東潤,土谷 亮,小野寺 秀俊

    電子情報通信学会ソサイエティ大会  2012.9 

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  • チップ内基板バイアス生成回路のモジュール化設計

    釡江典裕,土谷 亮,小野寺秀俊

    DA シンポジウム 2012   2012.8 

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  • Loss Modeling of On-Chip Transmission-Line for Millimeter-Wave and Terahertz Applications Invited International conference

    A. Tsuchiya

    Collaborative Conference on Materials Research  2012.6 

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  • Loss Modeling of On-Chip Transmission-Line for Millimeter-Wave and Terahertz Applications Invited International conference

    Collaborative Conference on Materials Research 2012  2012.6 

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  • Impact of radiation loss in on-chip transmission-line for terahertz applications International conference

    A. Tsuchiya, H. Onodera

    IEEE 16th Workshop on Signal and Power Integrity  2012.5 

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  • テラヘルツCMOSにおける配線モデル化の課題

    第29回シリコンアナログRF研究会  2012.5  電子情報通信学会

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  • インダクティブピーキングを用いた増幅回路に おける解析的ジッタ予測手法

    榎並達也, 宮脇成和, 土谷 亮, 小野寺秀俊

    電子情報通信学会総合大会  2012.3 

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  • 完全差動回路構成 GVCO の高速化設計

    川中 啓敬,岸根 桂路,土谷 亮,小野寺 秀俊

    電子情報通信学会総合大会  2012.3 

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  • 細粒度基板電圧制御に用いる DA 変換器

    釡江 典裕,土谷 亮,小野寺 秀俊

    電子情報通信学会総合大会  2012.3 

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  • Dual-PLL based on Temporal Redundancy for Radiation-Hardening あ

    SinNyoung Kim, A. Tsuchiya, H. Onodera

    第28回シリコンアナログRF研究会, Mar 2012.  2012.3 

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  • A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS International conference

    T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

    Asia and South Pacific Design Automation Conference  2012.1 

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  • 伝送線路の損失に対する異常表皮効果の影響

    土谷 亮, 小野寺秀俊

    電子情報通信学会技術研究報告  2011.12 

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  • Bandwidth Enhancement for High Speed Amplifier Utilizing Mutually Coupled On-Chip Inductors Invited International conference

    A. Tsuchiya, T. Kuboki, Y. Ohtomo, K. Kishine, S. Miyawaki, M. Nakamura, H. Onodera

    2011 International SoC Design Conference  2011.11 

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  • A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μ m CMOS International conference

    S. Miyawaki, M. Nakamura, A. Tsuchiya, K. Kishine, H. Onodera

    2011 International SoC Design Conference  2011.11 

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  • An area effective forward/reverse body bias generator for within-die variability compensation International conference

    N. Kamae, A. Tsuchiya, H. Onodera

    IEEE Asian Solid-State Circuits Conference  2011.11 

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  • Bandwidth Enhancement for High Speed Amplifier Utilizing Mutually Coupled On-Chip Inductors Invited International conference

    2011 International SoC Design Conference  2011.11  IEEK

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  • 配線モデル化におけるGrain Boundaryの影響

    土谷 亮, 小野寺 秀俊

    第27回 シリコンアナログRF研究会, Nov 2011.  2011.11 

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  • 100GHzを超える領域での配線損失に関する検討

    土谷 亮, 小野寺 秀俊

    第26回 シリコンアナログRF研究会, Aug 2011.  2011.8 

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  • Gradient resistivity method for numerical evaluation of anomalous skin Effect International conference

    A. Tsuchiya, H. Onodera

    IEEE 15th Workshop on Signal Propagation on Interconnects  2011.5 

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  • 異常表皮効果の数値的評価手法

    土谷 亮, 小野寺 秀俊

    第25回 シリコンアナログRF研究会, May 2011.  2011.5 

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  • Variation-sensitive monitor circuits for estimation of die-to-die process variation International conference

    A.K.M. Mahfuzul Islam, A. Tsuchiya, K. Kobayashi, H. Onodera

    IEEE International Conference on Microelectronic Test Structures  2011.4 

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  • Modeling of On-Chip Interconnects for mm-Wave and higher Frequency Application

    The 3rd Young Researchers International Symopium  2010.12  GCOE on Photonics and Electronics Science and Engineering

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  • 光と電気は融合可能か? Invited

    モデレータ: 益 一哉 (東工大), パネラー: 横山 新 (広島大), 大橋 啓之 (NEC, MIRAI-Selete), 菅原 俊樹 (日立中研), 石塚 裕康 (ルネサスエレクトロニクス), 土谷 亮 (京大)

    デザインガイア 2010  2010.11 

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  • オンチップ配線における異常表皮効果に関する検討

    土谷 亮, 小野寺 秀俊

    第24回 シリコンアナログRF研究会, Nov 2010.  2010.11 

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  • パネル討論 光と電気は融合可能か? Invited

    デザインガイア 2010  2010.11  情報処理学会

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  • A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18um CMOS International conference

    T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

    IEEE Custom Integrated Circuit Conference  2010.9 

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  • A design procedure of predictive RF MOSFET model for compatibility with ITRS International conference

    S.N. Kim, A. Tsuchiya, H. Onodera

    IEEE International SOC Conference  2010.9 

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  • MOS トランジスタの基板抵抗がインダクティブピーキング回路の周 波数特性に与える影響

    宮脇成和,土谷 亮,小野寺秀俊

    電子情報通信学会ソサイエティ大会  2010.9 

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  • 基板電圧の制御回路とその面積オーバヘッド

    釡江典裕,土谷 亮,小野寺秀俊

    電子情報通信学会ソサイエティ大会  2010.9 

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  • レイアウト制約が性能と製造性に与える影響

    北島和彦, 砂川洋輝, 土谷 亮, 小野寺秀俊

    DA シンポジウム 2010  2010.8 

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  • ミリ波帯における配線抵抗に関する考察

    土谷 亮, 小野寺 秀俊

    第23回 シリコンアナログRF研究会, Jul 2010.  2010.7 

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  • Measurement of on-chip transmission-line with stacked split-ring resonators International conference

    A. Tsuchiya, H. Onodera

    IEEE 14th Workshop on Signal Propagation on Interconnects  2010.5 

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  • ダミーフィルによる伝送損失増加の解析的評価手法

    土谷 亮, 小野寺 秀俊

    第22回 シリコンアナログRF研究会, Mar 2010.  2010.5 

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  • 複合インダクタを用いたLDドライバの設計

    久保木 猛, 大友 祐輔, 土谷 亮, 岸根 桂路, 小野寺 秀俊

    第22回シリコンアナログRF研究会, Mar 2010.  2010.5 

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  • Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability International conference

    A.K.M Mahfuzul Islam, A. Tsuchiya, K. Kobayashi, H. Onodera

    Tau Workshop 2010  2010.3 

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  • Transformer peakingにおける解析的設計手法

    宮脇 成和, 土谷 亮, 小野寺 秀俊

    第22回シリコンアナログRF研究会, Mar 2010.  2010.3 

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  • 相互結合インダクタを用いたTIA帯域向上手法

    奥村佳弘, 中村誠, 岸根桂路, 土谷 亮, 小野寺秀俊

    電子情報通信学会技術研究報告  2009.12 

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  • On-chip metamaterial transmission-line based on stacked split-ring resonator for millimeter-wave LSIs International conference

    A. Tsuchiya, H. Onodera

    Asia Pacific Microwave Conference  2009.11 

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  • Split-Ring Resonator を用いたチップ内メタ物質の構成に関する検討

    土谷 亮, 小野寺 秀俊

    第21回 シリコンアナログRF研究会, Nov 2009.  2009.11 

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  • ダミーフィルを考慮した伝送線路およびスパイラルインダクタの設計 (チュートリアル講演)

    土谷 亮, 小野寺 秀俊

    第21回 シリコンアナログRF研究会, Nov 2009.  2009.11 

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  • Effect of Dummy Fills on Characteristics of Passive Devices in CMOS Millimeter-Wave Circuits Invited International conference

    A. Tsuchiya, H. Onodera

    IEEE 8th International Conference on ASIC  2009.10 

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  • Effect of Dummy Fills on Characteristics of Passive Devices in CMOS Millimeter-Wave Circuits Invited International conference

    IEEE 8th International Conference on ASIC  2009.10  IEEE

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  • チップ内ばらつきが順序セルの動作特性に与える影響

    砂川洋輝,土谷 亮,小林和淑,小野寺秀俊

    DA シンポジウム 2009  2009.8 

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  • ダミーフィルがコプレーナ線路の特性に与える影響の位置依存性

    土谷 亮, 小野寺 秀俊

    第20回 シリコンアナログRF研究会, Jul 2009.  2009.7 

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  • Effect of underlayer dummy fills on on-chip transmission line International conference

    A. Tsuchiya, H. Onodera

    IEEE Workshop on Signal Propagation on Interconnects  2009.5 

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  • Effect of regularity-enhanced layout on printability and circuit performance of standard cells International conference

    H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashiy, H. Onodera

    10th International Symposium on Quality Electronic Design  2009.3 

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  • High performance on-chip differential signaling using passive compensation for global communication International conference

    L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E.S. Kuh, C.-K. Cheng

    Asia and South Pacific Design Automation Conference  2009.1 

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  • チップ内受動素子のモデリングにおける電磁界解析のノウハウ

    土谷 亮, 小野寺 秀俊

    第18回 シリコンアナログRF研究会, Dec 2008.  2008.12 

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  • Si-IC におけるダミーフィルを考慮した高周波受動素子のモデル化 Invited

    土谷 亮,小野寺 秀俊

    Microwave Workshops and Exhibition 2008  2008.11 

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  • Si-IC におけるダミーフィルを考慮した高周波受動素子のモデル化 Invited

    Microwave Workshops and Exhibition 2008  2008.11  電子情報通信学会

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  • ミリ波・準ミリ波帯におけるシリコン上のダミーメタルのスパイラルインダクタへの影響 Invited

    アジレント EEsof EDAフォーラム2008  2008.11  アジレントテクノロジー

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  • On-chip high performance signaling using passive compensation International conference

    Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, C.-K. Cheng

    26th IEEE International Conference on Computer Design  2008.10 

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  • オンチップ差動伝送線路の構造と下層配線からのノイズの関係

    久保木猛, 土谷 亮, 小野寺秀俊

    電子情報通信学会ソサイエティ大会  2008.9 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • CMOS ミリ波回路におけるオンチップ伝送線路のモデル化 Invited

    土谷 亮,小野寺 秀俊

    電子情報通信学会ソサイエティ大会  2008.9 

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    Language:Japanese   Presentation type:Oral presentation (invited, special)  

  • CMOSミリ波回路におけるオンチップ伝送線路のモデル化 Invited

    2008年電子情報通信学会ソサイエティ大会  2008.9  電子情報通信学会

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    Language:Japanese   Presentation type:Oral presentation (invited, special)  

  • スパイラルインダクタに対するダミーフィルおよび基板の影響比較

    土谷 亮, 小野寺 秀俊

    第17回 シリコンアナログRF研究会, Sep 2008.  2008.9 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • レイアウト規則性が回路性能とばらつきに及ぼす 影響の評価

    砂川洋輝, 寺田晴彦, 土谷 亮, 小林和淑, 小野寺秀俊

    DA シンポジウム 2008  2008.8 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • リングオシレータアレイによるゲート遅延ばら つきの評価とモデル化

    寺田晴彦, 土谷 亮, 小林和淑, 小野寺秀俊

    DA シンポジウム 2008  2008.8 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Dummy fill insertion considering the effect on high-frequency characteristics of spiral inductors International conference

    A. Tsuchiya, H. Onodera

    IEEE MTT-S International Microwave Symposium  2008.6 

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  • Education Delivery in the Design and Performance of Electrical Packaging and Interconnect International conference

    Moderator: Robert J. Evans, Panelist: T. R. Arabi, F. G. Canavero, M. Swaminathan, A. Tsuchiya

    12th IEEE Workshop on Signal Propagation on Interconnects  2008.5 

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    Language:English   Presentation type:Symposium, workshop panel (nominated)  

  • Education Delivery in the Design and Performance of Electrical Packaging and Interconnect Invited International conference

    12th IEEE Workshop on Signal Propagation on Interconnects  2008.5  IEEE

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    Language:English   Presentation type:Symposium, workshop panel (nominated)  

  • スパイラルインダクタ用くし形ダミーフィルの最適形状に関する検討

    土谷 亮, 小野寺 秀俊

    第16回 シリコンアナログRF研究会, May 2008.  2008.5 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • スパイラルインダクタの高周波特性に対する非正方形ダミーフィルの影響評価

    土谷 亮, 小野寺 秀俊

    第15回 シリコンアナログRF研究会, Feb 2008.  2008.2 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Statistical gate delay model for multiple input switching International conference

    T. Fukuoka, A. Tsuchiya, H. Onodera

    Asia and South Pacific Design Automation Conference  2008.1 

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  • Modeling of On-Chip Transmission-Lines ―Impact of Orthogonal Wires, Si Substrate and DummyFills― Invited

    A. Tsuchiya, Hidetoshi Onodera

    Microwave Workshops and Exhibition 2007  2007.11 

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    Language:Japanese   Presentation type:Oral presentation (invited, special)  

  • Modeling of On-Chip Transmission-Lines ---Impact of Orthogonal Wires, Si Substrate and Dummy Fills--- Invited

    Microwave Workshops and Exhibition 2007  2007.11  電子情報通信学会

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    Language:English   Presentation type:Public lecture, seminar, tutorial, course, or other speech  

  • スパイラルインダクタ周辺のダミーフィル挿入最適化の検討

    土谷 亮, 小野寺 秀俊

    第14回 シリコンアナログRF研究会, Nov 2007.  2007.11 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Effect of Dummy Fills on High frequency characteristics of Spiral Inductor International conference

    A. Tsuchiya, Hidetoshi Onodera

    14th Workshop on Synthesis And System Integration of Mixed Information technologies  2007.10 

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  • Analytical eye-diagram model for on-chip distortionless transmission lines and its application to design space exploration International conference

    M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng

    Custom Integrated Circuits Conference  2007.9 

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  • スパイラルインダクタの高周波特性への影響を考慮したダミーフィル挿入方法の検討

    土谷 亮, 小野寺 秀俊

    第13回 シリコンアナログRF研究会, Sep 2007.  2007.9 

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  • 統計的遅延解析における遅延分布間の最大値計算手法

    寺田晴彦, 福岡孝之, 土谷 亮, 小野寺秀俊

    DA シンポジウム 2007  2007.8 

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  • 同時スイッチングを考慮した統計的遅延解析

    福岡孝之, 土谷 亮, 小野寺秀俊

    DA シン ポジウム 2007  2007.8 

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  • Measurement of interconnect loss due to dummy fills International conference

    A. Tsuchiya, H. Onodera

    11th IEEE Workshop on Signal Propagation on Interconnects  2007.5 

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  • ダミーフィルが配線の高周波特性に与える影響

    土谷 亮, 小野寺 秀俊

    電子情報通信学会技術研究報告  2007.5 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • オンチップ差動伝送線路に対する下層配線の影響

    久保木 猛, 土谷 亮, 小野寺 秀俊

    第16回 シリコンアナログRF研究会, May 2007.  2007.5 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • ダミーフィルがオンチップ配線の高周波特性に与える影響の解析的評価手法

    土谷 亮, 小野寺 秀俊

    回路とシステム軽井沢ワークショップ  2007.4 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Worst-case delay analysis considering the variability of transistors and interconnects International conference

    T. Fukuoka, A. Tsuchiya, H. Onodera

    International Symposium on Physical Design  2007.3 

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  • オンチップ配線における配線抵抗変動要因の比較

    土谷 亮, 小野寺 秀俊

    第11回 シリコンアナログRF研究会, Mar 2007.  2007.3 

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  • A 10Gbps/channel on-chip signaling circuit with an impedance unmatched CML driver in 90nm CMOS technology International conference

    T. Kuboki, A. Tsuchiya, H. Onodera

    Asia and South Pacific Design Automation Conference  2007.1 

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    Language:English   Presentation type:Oral presentation (general)  

  • シャントコンダクタンスを挿入したオンチップ伝送線路特性評価

    Jangsombatsiri Siriporn, 橋本 昌宜, 土谷 亮, 尾上 孝雄

    第10回 シリコンアナログRF研究会, Nov 2006.  2006.11 

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  • ダミーフィルが配線特性に与える影響の実測による評価

    土谷 亮, 小野寺 秀俊

    第10回 シリコンアナログRF研究会, Nov 2006.  2006.11 

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  • Analytical estimation of interconnect loss due to dummy fills International conference

    A. Tsuchiya, H. Onodera

    Electrical Performance of Electronic Packaging  2006.10 

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  • 将来の微細プロセスにおけるDVSとPower Gatingの比較

    関良平, 土谷 亮, 小野寺秀俊

    電子情報通信学会ソサイエティ大会  2006.9 

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  • トランジスタと配線構造のばらつきを考慮した遅延時間のワーストケー ス解析

    福岡孝之, 土谷 亮, 小野寺秀俊

    DA シンポジウム 2006  2006.7 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Effect of dummy fills on high-frequency characteristics of on-chip interconnects International conference

    A. Tsuchiya, H. Onodera

    10th IEEE Workshop on Signal Propagation on Interconnects  2006.5 

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  • Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design International conference

    T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

    10th IEEE Workshop on Signal Propagation on Interconnects  2006.5 

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  • 0.15um試作PLLのジッタ要因解析

    濱田 隆行, 土谷 亮, 小野寺 秀俊

    第8回 シリコンアナログRF研究会, May 2006.  2006.5 

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  • ITRS準拠トランジスタモデルとPTMの比較

    土谷 亮, 上村 晋一郎, 小野寺 秀俊

    第8回 シリコンアナログRF研究会, May 2006.  2006.5 

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  • 出力インピーダンスの調整による高速信号伝送用CMLドライバの低 消費電力設計

    久保木 猛, 土谷 亮, 小野寺 秀俊

    回路とシステム軽井沢ワークショップ  2006.4 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • オンチップ長距離高速信号伝送の性能予測

    土谷 亮, 小野寺 秀俊

    回路とシステム軽 井沢ワークショップ  2006.4 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • 配線とトランジスタのばらつきを考慮したバッファの挿入方法

    福岡孝之, 土谷 亮, 小野寺秀俊

    電子情報通信学会総合大会  2006.3 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • ロードマップに準拠した SPICE トランジスタモデルの構 築

    上村晋一朗, 土谷 亮, 橋本昌宜, 小野寺秀俊

    電子情報通信学会総合大会  2006.3 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • オンチップ配線の高周波特性に対するダミーメタルの影響

    土谷 亮, 小野寺 秀俊

    第7回シリコンアナログRF研究会, Feb 2006.  2006.2 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Interconnect RL extraction at a single representative Frequency International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    Asia and South Pacific Design Automation Conference  2006.1 

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  • Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction International conference

    T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto

    International Workshop on Compact Modeling  2006.1 

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  • オンチップ配線の特性抽出におけるダミーメタルの影響

    土谷 亮, 小野寺 秀俊

    第6回シリコンアナログRF研究会  2005.11 

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  • CML を用いたオンチップ長距離高速信号伝送技術の開 発

    土谷 亮,新名 亮規,橋本 昌宜,小野寺 秀俊

    第9回システム LSI ワークショップ  2005.11 

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    Language:Japanese   Presentation type:Poster presentation  

  • Performance prediction of on-chip high throughput global signaling International conference

    M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera

    IEEE Topical Meeting on Electrical Performance of Electronic Packaging  2005.10 

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  • Design guideline for resistive termination of on-chip high-speed interconnects International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    Custom Integrated Circuits Conference  2005.9 

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  • 配線の伝達特性に基づく抽出周波数決定手法

    土谷 亮,橋本 昌宜,小野寺 秀俊

    DA シンポジウム 2005  2005.8 

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  • 実測と電磁界解析による基板損失の評価

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    第3回シリコンアナログRF研究会, Jan 2005.  2005.6 

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  • Substrate loss of on-chip transmission-lines with power/ground wires in lower layer International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    9th IEEE Workshop on Signal Propagation on Interconnects  2005.5 

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  • Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    2005 International Meeting for Future Electron Devices, Kansai  2005.4 

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  • オンチップ高速信号伝送における終端抵抗決定手法

    土谷 亮,橋本 昌宜,小野寺 秀俊

    第 18 回 回路 とシステム軽井沢ワークショップ  2005.4 

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  • オンチップ伝送線路の基板損失に対する下層配線の影響

    土谷 亮, 橋本昌宜, 小野寺秀俊

    電子情報通信学会総合大会  2005.3 

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  • オンチップ高速信号伝送用線路の解析的性能評価

    土谷 亮,橋本 昌宜,小野寺 秀俊

    電子情報通信学会技術研究報告  2005.3 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Return path selection for loop RL extraction International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    Asia and South Pacific Design Automation Conference  2005.1 

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  • Performance Prediction of On-chip Global Signaling International conference

    M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera

    3rd Electrical Design of Avdanced Packaging and Systems Workshop  2004.11 

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  • On-chip global signaling by wave pipelining International conference

    M. Hashimoto, A. Tsuchiya, H. Onodera

    IEEE Topical Meeting on Electrical Performance of Electronic Packaging  2004.10 

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  • Performance limitation of on-chip global interconnects for high-speed signaling International conference

    A. Tsuchiya, Y. Gotoh, M. Hashimoto, H. Onodera

    Custom Integrated Circuits Conference  2004.9 

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  • 基板および周辺信号配線が配線特性に及ぼす影響の実測

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    第2回シリコンアナログRF研究会, Aug 2004.  2004.8 

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  • 配線 RL 抽出におけるリターンパス選択手法

    土谷 亮,橋本 昌宜,小野寺 秀俊

    DA シンポジウム 2004  2004.7 

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  • オンチップ伝送線路のリターン電流分布が信号波形に与える影響 — 平衡・不平衡伝送の比較 —

    土谷 亮,橋本 昌宜,小野寺 秀俊

    第17回 回路とシステム軽井沢ワークショップ  2004.4 

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  • オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響

    土谷 亮, 橋本 昌宜, 小野寺 秀俊

    第1回シリコンアナログRF研究会, Apr 2004.  2004.4 

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  • Representative frequency for interconnect R(f)L(f)C extraction International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    Asia and South Pacific Design Automation Conference  2004.1 

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  • 直交配線を持つオンチップ伝送線路の特性評価

    土谷 亮,橋本 昌宜,小野寺 秀俊

    DA シンポジウム 2003  2003.7 

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  • Frequency Determination for Interconnect RLC Extraction International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    11th Workshop on Synthesis And System Integration of Mixed Information technologies  2003.4 

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  • 配線 R(f)L(f)C 抽出のための代表周波数決定手法

    土谷 亮,橋本 昌宜,小野寺 秀俊

    第16回 回路と システム軽井沢ワークショップ  2003.4 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Interconnect Structures for High-Speed Long-Distance Signal Transmission International conference

    M. Hashimoto, D. Hiramatsu, A. Tsuchiya, H. Onodera

    15th Annual IEEE International ASIC/SOC Conference  2002.9 

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  • 長距離高速信号伝送を可能にする VLSI 配線構造の検討

    平松 大輔,土谷 亮,橋本 昌宜,小野寺 秀俊

    DA シンポジウム 2002  2002.7 

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    Language:Japanese   Presentation type:Oral presentation (general)  

  • Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects International conference

    A. Tsuchiya, M. Hashimoto, H. Onodera

    10th Workshop on Synthesis And System Integration of Mixed Information technologies  2001.10 

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  • VLSI 配線の伝送線路化を考慮した駆動力決定手法

    土谷 亮,小野寺 秀俊

    DA シンポジウム 2001  2001.7 

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Teaching Experience

  • 人間探求学(電子システム)

    2020.4 Institution:滋賀県立大学

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    Level:Undergraduate (liberal arts) 

  • 電磁波工学

    2018.10 Institution:滋賀県立大学

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    Level:Undergraduate (specialized) 

  • 電気電子設計製図

    2018.4 Institution:滋賀県立大学

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    Level:Undergraduate (specialized) 

  • 電子システム工学実験Ⅳ

    2018.4 Institution:滋賀県立大学

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    Level:Undergraduate (specialized) 

  • 無線システム工学

    2018.4 Institution:滋賀県立大学

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    Level:Postgraduate 

  • 電子回路Ⅰ

    2017.10 Institution:滋賀県立大学

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    Level:Undergraduate (specialized) 

  • 電子システム工学実験Ⅱ

    2017.4 Institution:滋賀県立大学

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    Level:Undergraduate (specialized) 

  • 制御工学

    2017.4 Institution:滋賀県立大学

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    Level:Undergraduate (specialized) 

  • 電気電子工学実習B

  • 電気電子工学実験B

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Social Contribution

  • 第1回ハンズオンセミナー Siliwiz で知識0から始めるIC設計

    Role(s): Lecturer

    ISHI会  技研ベース,オンライン  2023.5

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    Audience: College students, Graduate students, Researchesrs, Company

    Type:Lecture

  • IEEE SSCS PICO Program Chipathon 2023 Volunteer

    Role(s): Advisor

    IEEE Solid-State Circuits Society  Chipathon 2023  Online  2023.1 - 2023.12

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    Audience: College students, Graduate students, Teachers, Researchesrs, Scientific

    Type:Seminar, workshop

  • 令和元年度 現代科学研修

    Role(s): Lecturer

    滋賀県総合教育センター  令和元年度 現代科学研修  滋賀県立大学  2019.8

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    Audience: Teachers

    Type:Other

    集積システムとトランジスタ回路について(講義・実習)

  • 確率・統計再勉強

    Role(s): Lecturer

    電子情報通信学会  2019年 ICD夏の合宿  2019.7

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    Audience: Graduate students, Researchesrs

  • アジレント EEsof EDAフォーラム

    Role(s): Lecturer

    アジレント・テクノロジー  2008.4

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    Audience: Researchesrs, General

Media Coverage

Academic Contribution

  • 科学技術専門家ネットワーク 専門調査委員

    文部科学省科学技術政策研究所科学技術動向研究センター  2014.4

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    Type:Academic research