Papers - TSUCHIYA Akira
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Cryogenic and RF Modeling of On-Chip Passive Devices for Quantum Computer Invited Reviewed
Akira Tsuchiya
IEEE 17th International Conference on Solid-State and Integrated Circuit Technology 1 - 3 2024.10
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Activities for Open-Source Integrated Circuits Design in Japan Invited Reviewed
Akira Tsuchiya
130 - 133 2024.6
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Mean-Free-Path-Based Evaluation of Size Effectand Anomalous Skin Effect in On-Chip Interconnects under Cryogenic Environment Reviewed
Akira Tsuchiya
28th IEEE Workshop on Signal and Power Integrity 1 - 4 2024.5
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A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks Reviewed International journal
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
Microelectronics Journal 2024.3
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A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip Reviewed
T. Inoue, A. Tsuchiya, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura
IEEE Transactions on Circuits and Systems II 2024
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High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS Invited Reviewed
Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
IEEE 15th International Conference on ASIC 2023.10
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4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS Reviewed
Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
The 20th International SoC Conference (ISOCC) 2023.10
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Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process Reviewed
Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
IEICE Electronics Express 20 ( 18 ) 2023.9
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10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks Reviewed
Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
IEICE Electronics Express 20 ( 14 ) 2023.7
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A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS Reviewed
T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura
IEEE International Conference on Electronics, Circuits and Systems (ICECS) 1 - 4 2023
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4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS Reviewed
D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya and K. Kishine
International SoC Design Conference (ISOCC) 13 - 14 2023
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A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS Reviewed International journal
Inoue T., Tsuchiya A., Kishine K., Ito D., Takahashi Y., Nakamura M.
ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 1 - 4 2022.10
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A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band Reviewed International journal
Inoue M., Nakashioya S., Inoue T., Tsuchiya A., Kishine K.
ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 1 - 4 2022.10
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A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA Reviewed International journal
Okamoto M., Inoue T., Tsuchiya A., Kishine K.
Proceedings - International SoC Design Conference 2022, ISOCC 2022 55 - 56 2022.10
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Smart Computational Resource Distribution System with Automatic Classification Interface for CPS Reviewed International journal
Teramura Y., Inoue T., Tsuchiya A., Kishine K.
Proceedings - International SoC Design Conference 2022, ISOCC 2022 101 - 102 2022.10
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Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing Reviewed International journal
Shimohane S., Inoue T., Tsuchiya A., Kishine K.
Proceedings - International SoC Design Conference 2022, ISOCC 2022 338 - 339 2022.10
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A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS Reviewed International journal
T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura
65th IEEE International Midwest Symposium on Circuits and Systems 1 - 4 2022.8
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A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad Reviewed International journal
A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura
IEEE 65th International Midwest Symposium on Circuits and Systems 1 - 4 2022.8
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Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit Reviewed
Takahashi Y., Ito D., Namamura M., Tsuchiya A., Inoue T., Kishine K.
Electronics (Switzerland) 11 ( 6 ) 2022.3
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Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion Reviewed International journal
Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine
International Conference on Electronics, Information, and Communication 579 - 582 2022.2
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A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver Reviewed International journal
Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine
International Conference on Electronics, Information, and Communication 644 - 647 2022.2
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Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems Reviewed International journal
Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine
International Conference on Electronics, Information, and Communication 616 - 619 2022.2
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Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier Reviewed International journal
Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, and Makoto Nakamura
International Conference on Electronics, Information, and Communication 640 - 643 2022.2
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Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS Reviewed International journal
Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
The 27th Asia and South Pacific Design Automation Conference 96 - 97 2022.1
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A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks Reviewed International journal
T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura
28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) 1 - 6 2021.11
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Dynamic Memory Access Control for Accelerating FPGA-based Image Processing Reviewed International journal
Kenta Nishiguchi, Toshiyuki Inoue, Rei Yamazaki, Kazunori Ogohara, Akira Tsuchiya, Keiji Kishine
Journal of Semiconductor Technology and Science 21 ( 1 ) 29 - 38 2021.2
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5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS Reviewed
Ichii Y., Inoue T., Tsuchiya A., Kishine K.
2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021.1
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Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA Reviewed
Yoshimura U., Inoue T., Tsuchiya A., Kishine K.
2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021.1
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Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers Reviewed International journal
Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
Asia-South Pacific Design Automation Conference 15 - 16 2021.1
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A Method for Accelerating the Inference Process of FPGA-based LSTM for Biometric Systems Reviewed
Yoshimura U., Inoue T., Tsuchiya A., Kishine K.
IEIE Transactions on Smart Processing and Computing 10 ( 5 ) 416 - 423 2021.1
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Processing Time Reduction for JPEG Compression Using Pixel Array Conversion Reviewed International journal
Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
17th International SoC Design Conference 2020.10
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Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Reviewed International journal
Akira TSUCHIYA, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, Hidetoshi ONODERA
IEiCE Transactions on Electronics E103-C ( 10 ) 489 - 496 2020.10
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Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking Invited Reviewed International journal
Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2020 IEEE International Symposium on Radio-Frequency Integration Technology 12 - 14 2020.9
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Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS Reviewed
Inoue T., Tsuchiya A., Kishine K.
Journal of Semiconductor Technology and Science 20 ( 2 ) 177 - 186 2020.4
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Capacitive Sensor for Contact Angle Estimation of Droplet on Microfluidic Chip Reviewed International journal
Akira Tsuchiya, Toshiyuki Inoue and Keiji Kishine
2019 Asia-Pacific Microwave Conference 2019.12
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Frequency Discriminator Using a Simple AD Converter for Interface Systems Reviewed International journal
Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine
16th International SoC Design Conference 2019.10
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Optimization Technique of Memory Traffic for FPGA-Based Image Processing System Reviewed International journal
Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara and Keiji Kishine
16th International SoC Design Conference 2019.10
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Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS Reviewed International journal
Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine
16th International SoC Design Conference 2019.10
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A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Reviewed International journal
Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
32nd International System-on-Chip Conference 2019.9
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Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier Reviewed International journal
Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine
32nd IEEE International System-on-Chip Conference 2019.9
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Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity Reviewed
Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA
IEICE TRANSACTIONS on Electronics E102-C ( 7 ) 573 - 579 2019.7
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FPGA-based binary labeling signal transmission system Reviewed
Inoue T., Nomura K., Noguchi R., Koda N., Tsuchiya A., Kishine K.
Journal of Semiconductor Technology and Science 19 ( 3 ) 276 - 286 2019.6
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A 25-Gb/s Low-Power Clock and Data Recovery with an ActiveStabilizing CML-CMOS Conversion Reviewed International journal
Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
The 25th IEEE International Conference on Electronics Circuits and Systems 2018.12
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A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-less Bandwidth Compensation Reviewed International journal
Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
IEEE Asian Solid-State Circuits Conference 69 - 72 2018.11
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Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback Reviewed International journal
Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, and Hidetoshi Onodera
The 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2018) 2018.8
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Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net Reviewed International journal
Akira TSUCHIYA, Akitaka HIRATSUKA, Toshiyuki INOUE, Keiji KISHINE, Hidetoshi ONODERA
IEEE Workshop on Signal and Power Integrity 1 - 4 2018.5
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A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS Reviewed International journal
Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka
International Symposia on VLSI Design, Automation and Test 2018.4
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Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS Reviewed International journal
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura
International SoC Design Conference 2017.11
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FPGA-Based Transceiver Circuit for Labeling Signal Transmission System Reviewed International journal
Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
International SoC Design Conference 2017.11
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Compact Implementation IIR Filter in FPGA for Noise Reduction of Sensor Signal Reviewed International journal
Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
International SoC Design Conference 2017.11
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Power-Bandwidth Trade-Off Analysis of Multi-Stage Inverter-Type Transimpedance Amplifier for Optical Communication Reviewed International journal
Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera
MWSCAS2017 2017.8
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A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS Reviewed International journal
T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto
IEIE Transactions on Smart Signal and Computing 5 ( 3 ) 207 - 214 2016.6
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A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS Reviewed
T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto
IEIE Transactions on Smart Signal and Computing 5 ( 3 ) 207 - 214 2016.6
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A 32-Gb/s output buffer circuit with doubled pre-emphasis in 65-nm CMOS Reviewed
T. Tanaka, K. Kishine, D. Omoto, A. Tsuchiya, H. Inaba
International Conference on Electronics, Information, and Communication 2016.1
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A 25-Gb/s 480-mW CMOS Modulator Driver Using Area-Efficient 3D Inductor Peaking Reviewed
Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura
IEEE Asian Solid-State Circuits Conference 2015.11
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A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage Reviewed
N. Kamae, A. Tsuchiya, H. Onodera
IEICE Transactions on Electronics 98-C ( 6 ) 504 - 511 2015.6
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A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage Reviewed
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
IEICE TRANSACTIONS ON ELECTRONICS E98C ( 6 ) 504 - 511 2015.6
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Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS Reviewed
K. Kishine, H. Inaba, H. Inoue, M. Nakamura, A. Tsuchiya, H. Katsurai, H. Onodera
IEEE Transactions on Circuits and Systems I 62 ( 5 ) 1288 - 1295 2015.5
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A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS Reviewed
Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 62 ( 5 ) 1288 - 1295 2015.5
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A wireless neural recording system with a precision motorized microdrive for freely behaving animals Reviewed International journal
T. Hasegawa, H. Fujimoto, K. Tashiro, M. Nonomura, A. Tsuchiya, D. Watanabe
Scientific Reports 5 ( 7853 ) 2015.1
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A wireless neural recording system with a precision motorized microdrive for freely behaving animals Reviewed
Taku Hasegawa, Hisataka Fujimoto, Koichiro Tashiro, Mayu Nonomura, Akira Tsuchiya, Dai Watanabe
SCIENTIFIC REPORTS 5 7853 2015.1
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Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation Reviewed
Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) 181 - 185 2015
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PLL の物理レイアウト自動生成を目指した設計手法 Reviewed
釡江典裕, 土谷亮, 石原亨, 小野寺秀俊
情 報処理学会DA シンポジウム 2014.8
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Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure Reviewed
SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
IEICE TRANSACTIONS ON ELECTRONICS E97C ( 4 ) 325 - 331 2014.4
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Analysis of radiation-induced clock-perturbation in phase-locked Loop Reviewed
S.N. Kim, A. Tsuchiya, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 3 ) 768 - 776 2014.3
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A body bias generator with low supply voltage for within-die variability compensation Reviewed
N. Kamae, A. Tsuchiya, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 3 ) 734 - 740 2014.3
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A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation Reviewed
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 3 ) 734 - 740 2014.3
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Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop Reviewed
SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 3 ) 768 - 776 2014.3
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Radiation-hardened PLL with a switchable dual modular redundancy structure Reviewed
S.N. Kim, A. Tsuchiya, H. Onodera
IEICE Transactions on Electronics E97-C ( 4 ) 325 - 331 2014.1
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25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS Reviewed
Tomoki Tanaka, Keiji Kishine, Hiromi Inaba, Akira Tsuchiya
2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 94 - 95 2014
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A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops Reviewed
Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai
2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 2704 - 2707 2014
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A Body Bias Generator with Wide Supply-Range down to Threshold Voltage for Within-Die Variability Compensation Reviewed
Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Hidetoshi Onodera
2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) 53 - 56 2014
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\Analysis of Radiation-Induced Timing Vulnerability on Phase- locked Loops Reviewed
S.N. Kim, A. Tsuchiya, H. Onodera
情報処理学会DA シンポジウム 2013.8
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A 25-Gb/s LD Driver with Area-Effective Inductor in a 0.18-mu m CMOS Reviewed
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 105 - 106 2013
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Perturbation-immune radiation-hardened PLL with a switchable DMR structure Reviewed
Sin Nyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013 128 - 132 2013
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Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits Reviewed
Akira Tsuchiya, Hidetoshi Onodera
IMFEDK 2013 - 2013 International Meeting for Future of Electron Devices, Kansai 106 - 107 2013
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Advanced RF and analog integrated circuits for fourth generation wireless communications and beyond Reviewed
Ramesh Pokharel, Leonid Belostotski, Akira Tsuchiya, Ahmed Allam, Mohammad S. Hashmi
International Journal of Microwave Science and Technology 2013
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A slow-wave transmission line with thin pillars for millimeter-wave CMOS Reviewed
Taro Amagai, Akira Tsuchiya, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera
2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013 2013
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Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation Reviewed International journal
A. K. M. Mahfuzul Islam, A. Tsuchiya, K. Kobayashi, H. Onodera
IEEE Transactions on Semiconductor Manufacturing 25 ( 4 ) 571 - 580 2012.11
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A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation Reviewed
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
IEEE Asian Solid-State Circuits Conference(A-SSCC) 2012, pp. 389-392, Nov 2012. 2012.11
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Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation Reviewed
Islam A. K. M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 25 ( 4 ) 571 - 580 2012.11
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Dual-PLL based on Temporal Redundancy for Radiation-Hardening Reviewed
SinNyoung KIM, Akira TSUCHIYA, Hidetoshi ONODERA
Proceedings of 10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications 2012.10
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Modeling of Single-Event Failures in Dividerand PFD of PLLs based on Jitter Analysis Reviewed
SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
13th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2012. 2012.9
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チップ内基板バイアス生成回路のモジュール化設計 Reviewed
釡江典裕, 土谷亮, 小野寺秀俊
情報処理学会DAシンポジウム2012論文集, pp. 55-60, Aug 2012. 2012.8
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Area-effective inductive peaking with interwoven inductor for high-speed laser-diode driver for optical communication system Reviewed
T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95-A ( 2 ) 479 - 486 2012.2
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Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System Reviewed
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 2 ) 479 - 486 2012.2
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A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18μm CMOS Reviewed
T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 561 - 562 2012
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Impact of radiation loss in on-chip transmission-line for terahertz applications Reviewed
Akira Tsuchiya, Hidetoshi Onodera
2012 IEEE 16th Workshop on Signal and Power Integrity, SPI 2012 - Proceedings 125 - 128 2012
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A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μm CMOS Reviewed
S. Miyawaki, M. Nakamura, A. Tsuchiya, K. Kishine, H. Onodera
2011 International SoC Design Conference, ISOCC 2011 223 - 226 2011
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An area effective forward/reverse body bias generator for within-die variability compensation Reviewed
Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011 217 - 220 2011
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Gradient Resistivity Method for Numerical Evaluation of Anomalous Skin Effect Reviewed
Akira Tsuchiya, Hidetoshi Onodera
2011 15TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS (SPI) 139 - 142 2011
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Variation-sensitive monitor circuits for estimation of die-to-die process variation Reviewed
I.A.K.M. Mahfuzul, A. Tsuchiya, K. Kobayashi, H. Onodera
IEEE International Conference on Microelectronic Test Structures 153 - 157 2011
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レイアウト制約が性能と製造性に与える影響 Reviewed
北島和彦, 砂川洋輝, 土谷亮, 小野寺秀俊, 小野寺秀俊
情報処理学会DAシンポジウム論文集 2010 ( 7 ) 221 - 226 2010.8
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Effect of regularity-enhanced layout on variability and circuit performance of standard cells Reviewed
H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, H. Onodera
IPSJ Transactions on System LSI Design Methodology 3 130 - 139 2010.2
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A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18-mu m CMOS Reviewed
Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 2010
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Measurement of on-chip transmission-line with stacked split-ring resonators Reviewed
Akira Tsuchiya, Hidetoshi Onodera
2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings 137 - 140 2010
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Effect of regularity-enhanced layout on variability and circuit performance of standard cells Reviewed
Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
IPSJ Transactions on System LSI Design Methodology 3 130 - 139 2010
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A design procedure of predictive RF MOSFET model for compatibility with ITRS Reviewed
Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
Proceedings - IEEE International SOC Conference, SOCC 2010 396 - 399 2010
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A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-μm CMOS Reviewed
T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera
Proceedings of the Custom Integrated Circuits Conference 2010
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Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability Reviewed
A.K.M Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
Tau Workshop 2010, Mar 2010. 2010
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Statistical gate delay model for multiple input switching Reviewed
T. Fukuoka, A. Tsuchiya, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 12 ) 3070 - 3078 2009.12
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Statistical Gate Delay Model for Multiple Input Switching Reviewed
Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3070 - 3078 2009.12
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チップ内ばらつきが順序セルの動作特性に与える影響 Reviewed
砂川洋輝, 土谷亮, 小林和淑, 小野寺秀俊
情報処理学会DA シンポジウム 2009.8
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Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells Reviewed
Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2 195 - 200 2009
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On-Chip Metamaterial Transmission-Line Based on Stacked Split-Ring Resonator for Millimeter-Wave LSIs Reviewed
Akira Tsuchiya, Hidetoshi Onodera
APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 1458 - 1461 2009
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High performance on-chip differential signaling using passive compensation for global communication Reviewed
L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E.S. Kuh, C.-K. Cheng
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 385 - 390 2009
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Effect of underlayer dummy fills on on-chip transmission line Reviewed
A. Tsuchiya, H. Onodera
2009 IEEE Workshop on Signal Propagation on Interconnects, SPI \\'09 2009
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Analytical eye-diagram model for on-chip distortionless transmission lines and its application to design space exploration Reviewed
M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A ( 12 ) 3474 - 3480 2008.12
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Patterned floating dummy fill for on-chip spiral inductor considering the effect of dummy fill Reviewed International journal
A. Tsuchiya, H. Onodera
IEEE Transactions on Microwave Theory and Techniques 56 ( 12 ) 3217 - 3222 2008.12
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Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration Reviewed
Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 12 ) 3474 - 3480 2008.12
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Patterned Floating Dummy Fill for On-Chip Spiral Inductor Considering the Effect of Dummy Fill Reviewed
Akira Tsuchiya, Hidetoshi Onodera
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 56 ( 12 ) 3217 - 3222 2008.12
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Accurate estimation of the worst-case delay in statistical static timing analysis Reviewed
H. Terada, T. Fukuoka, A. Tsuchiya, H. Onodera
IPSJ Transactions on System LSI Design Methodology 1 116 - 125 2008.8
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Accurate estimation of the worst-case delay in statistical static timing analysis Reviewed
Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
IPSJ Transactions on System LSI Design Methodology 1 116 - 125 2008.8
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リングオシレータアレイによるゲート遅延ばらつきの評価とモデル化 Reviewed
寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊
情報処理学会DAシンポジウム論文集 2008 ( 7 ) 199 - 204 2008.8
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レイアウト規則性が回路性能とばらつきに及ぼす影響の評価 Reviewed
砂川洋輝, 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊
情報処理学会DAシンポジウム論文集 2008 ( 7 ) 67 - 72 2008.8
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Dummy fill insertion considering the effect on high-frequency characteristics of spiral inductors Reviewed
A. Tsuchiya, H. Onodera
IEEE MTT-S International Microwave Symposium Digest 787 - 790 2008
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On-chip high performance signaling using passive compensation Reviewed
Z. Yulei, Z. Ling, A. Tsuchiya, M. Hashimoto, C.-K. Cheng
26th IEEE International Conference on Computer Design 2008, ICCD 182 - 187 2008
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Statistical gate delay model for multiple input switching Reviewed
T. Fukuoka, A. Tsuchiya, H. Onodera
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 286 - 291 2008
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同時スイッチングを考慮した統計的遅延解析 Reviewed
福岡孝之, 土谷亮, 小野寺秀俊
情報処理学会DAシンポジウム論文集 2007 ( 7 ) 13 - 18 2007.8
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統計的遅延解析における遅延分布間の最大値計算手法 Reviewed
寺田晴彦, 福岡孝之, 土谷亮, 小野寺秀俊
情報処理学会DAシンポジウム論文集 2007 ( 7 ) 7 - 12 2007.8
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Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling Reviewed
A. Tsuchiya, M. Hashimoto, H. Onodera
IEICE Transactions on Electronics E90-C ( 6 ) 1267 - 1273 2007.6
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Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed
T. Kuboki, A. Tsuchiya, H. Onodera
IEICE Transactions on Electronics E90-C ( 6 ) 1274 - 1281 2007.6
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Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed
Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera
IEICE TRANSACTIONS ON ELECTRONICS E90C ( 6 ) 1274 - 1281 2007.6
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Analytical estimation of interconnect loss due to dummy fills Reviewed
20 19 - 22 2007.4
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A 10Gbps/channel on-chip signaling circuit with an impedance-unmatched CML driver in 90nm CMOS technology Reviewed
T. Kuboki, A. Tsuchiya, H. Onodera
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 120 - 121 2007
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Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration Reviewed
Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 869 - 872 2007
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Measurement of interconnect loss due to dummy fills Reviewed
Akira Tsuchiya, Hidetoshi Onodera
2007 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS 241 - 244 2007
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Effect of dummy fills on high-frequency characteristics of on-chip interconnects Reviewed
Akira Tsuchiya, Hidetoshi Onodera
Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006 275 - 278 2007
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Effect of Dummy Fills on High frequency characteristics of Spiral Inductor Reviewed
Akira Tsuchiya, Hidetoshi Onodera
14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007), pp.256-260, Oct 2007. 2007
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006 227 - 230 2007
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Worst-case delay analysis considering the variability of transistors and interconnects Reviewed
T. Fukuoka, A. Tsuchiya, H. Onodera
Proceedings of the International Symposium on Physical Design 35 - 42 2007
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 12 ) 3560 - 3568 2006.12
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Interconnect RL extraction based on transfer characteristics of transmission-line Reviewed
A. Tsuchiya, M. Hashimoto, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 12 ) 3585 - 3593 2006.12
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Interconnect RL extraction based on transfer characteristics of transmission-line Reviewed
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3585 - 3593 2006.12
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Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed
Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3560 - 3568 2006.12
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トランジスタと配線構造のばらつきを考慮した遅延時間のワーストケース解析 Reviewed
福岡孝之, 土谷亮, 小野寺秀俊
情報処理学会DAシンポジウム論文集 2006 ( 7 ) 13 - 18 2006.7
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Performance prediction of on-chip high-speed signaling Reviewed
19 393 - 398 2006.4
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Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed
19 387 - 392 2006.4
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Alternate self-shielding for high-speed and reliable on-chip global interconnect Reviewed
Y. Yuyama, A. Tsuchiya, K. Kobayashi, H. Onodera
IEICE Transactions on Electronics E89-C ( 3 ) 327 - 333 2006.3
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Alternate self-shielding for high-speed and reliable on-chip global interconnect Reviewed
Y Yuyama, A Tsuchiya, K Kobayashi, H Onodera
IEICE TRANSACTIONS ON ELECTRONICS E89C ( 3 ) 327 - 333 2006.3
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Analytical estimation of interconnect loss due to dummy fills Reviewed
A. Tsuchiya, H. Onodera
Electrical Performance of Electronic Packaging, EPEP 149 - 152 2006
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Low-Power Design of CML Drivers for On-Chip Transmission-Lines Reviewed
Akira Tsuchiya, Takeshi Kuboki, Hidetoshi Onodera
SASIMI2006,pp. 177-182 2006
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Interconnect RL extraction at a single representative frequency Reviewed
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 515 - 520 2006
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Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction Reviewed
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
International Workshop on Compact Modeling, pp. 51-56, 2006. 2006
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A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection
Akira Tsuchiya
2005.11
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A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection Reviewed
TSUCHIYA Akira
Kyoto University 2005.11
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CMLを用いたオンチップ長距離高速信号伝送技術の開発
土谷 亮, 新名 亮規, 橋本 昌宜, 小野寺 秀俊
第9回システムLSIワークショップ, pp.275--278, Nov 2005. 2005.11
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Performance Limitation of On-chip Global Interconnects for High-speed Signaling Reviewed
A. Tsuchiya, M. Hashimoto, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 4 ) 885 - 891 2005.4
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Design guideline for resistive termination of on-chip high-speed interconnects Reviewed
A. Tsuchiya, M. Hashimoto, H. Onodera
Proceedings of the Custom Integrated Circuits Conference 2005 608 - 611 2005
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Performance prediction of on-chip high-throughput global signaling Reviewed
Masanori Hashimoto, Akira Tsuchiya, Akinori Shinmyo, Hidetoshi Onodera
IEEE Topical Meeting on Electrical Performance of Electronic Packaging 2005 79 - 82 2005
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Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics Reviewed
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005. 2005
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Return path selection for loop RL extraction Reviewed
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 2 1078 - 1081 2005
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配線の伝達特性に基づく抽出周波数決定手法 Reviewed
土谷 亮, 橋本 昌宜, 小野寺 秀俊
DAシンポジウム 2005, pp.169-174, Aug 2005. 2005
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オンチップ高速信号伝送における終端抵抗決定手法 Reviewed
土谷 亮, 橋本 昌宜, 小野寺 秀俊
第18回 回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005. 2005
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Substrate loss of on-chip transmission-lines with power/ground wires in lower layer Reviewed
A Tsuchiya, M Hashimoto, H Onodera
SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS 2005 201 - 202 2005
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On-chip global signaling by wave pipelining Reviewed
M Hashimoto, A Tsuchiya, H Onodera
ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING 311 - 314 2004
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Performance Prediction of On-chip Global Signaling Reviewed
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
3rd Electrical Design of Avdanced Packaging and Systems Workshop, pp.87-100, Nov 2004. 2004
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Performance limitation of on-chip global interconnects for high-speed signaling Reviewed
A. Tsuchiya, Y. Gotoh, M. Hashimoto, H. Onodera
Proceedings of the Custom Integrated Circuits Conference 489 - 492 2004
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Representative frequency for interconnect R(f)L(f)C extraction Reviewed
A. Tsuchiya, M. Hashimoto, H. Onodera
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 691 - 696 2004
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配線RL抽出におけるリターンパス選択手法 Reviewed
土谷 亮, 橋本 昌宜, 小野寺 秀俊
DAシンポジウム 2004, pp.175-180, Jul 2004. 2004
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オンチップ伝送線路のリターン電流分布が信号波形に与える影響 — 平衡・不平衡伝送の比較 — Reviewed
土谷 亮, 橋本 昌宜, 小野寺 秀俊
第17回 回路とシステム軽井沢ワークショップ, pp.567-572, Apr 2004. 2004
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Representative Frequency for Interconnect R(f)L(f)C Extraction Reviewed
A. Tsuchiya, M. Hashimoto, H. Onodera
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E86-A ( 12 ) 2942 - 2951 2003.12
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Representative frequency for interconnect R(f)L(f)C extraction Reviewed
A Tsuchiya, M Hashimoto, H Onodera
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 12 ) 2942 - 2951 2003.12
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周辺配線の影響を考慮したオンチップ高速信号伝送用配線構造
土谷 亮
2003.3
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周辺配線の影響を考慮したオンチップ高速信号伝送用配線構造 Reviewed
土谷 亮
京都大学 2003.2
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Frequency Determination for Interconnect RLC Extraction Reviewed
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2003), pp.288-293, Apr 2003. 2003
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直交配線を持つオンチップ伝送線路の特性評価 Reviewed
土谷 亮, 橋本 昌宜, 小野寺 秀俊
DA シンポジウム 2003, pp.133-138, Jul 2003. 2003
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配線R(f)L(f)C抽出のための代表周波数決定手法 Reviewed
土谷 亮, 橋本 昌宜, 小野寺 秀俊
第16回 回路とシステム軽井沢ワークショップ, pp.61-66, Apr 2003. 2003
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VLSI 配線の伝送線路特性を考慮した駆動力決定手法 Reviewed
土谷亮, 橋本昌宜, 小野寺秀俊
情報処理学会論文誌 43 ( 5 ) 1338 - 1347 2002.5
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Interconnect Structures for High-Speed Long-Distance Signal Transmission Reviewed
M. Hashimoto, D. Hiramatsu, A. Tsuchiya, H. Onodera
15th Annual IEEE International ASIC/SOC Conference, pp. 426--430, Sep 2002. 2002
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VLSI配線の伝送線路特性を考慮した駆動力決定手法 Reviewed
土谷 亮, 橋本 昌宜, 小野寺 秀俊
情報処理学会論文誌 2002
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長距離高速信号伝送を可能にするVLSI配線構造の検討 Reviewed
平松 大輔, 土谷 亮, 橋本 昌宜, 小野寺 秀俊
DA シンポジウム 2002, pp.155-160, Jul 2002. 2002
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Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects Reviewed
Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
10th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2001), pp.377-381, Oct 2001. 2001
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VLSI配線の伝送線路化を考慮した駆動力決定手法 Reviewed
土谷 亮, 小野寺 秀俊
DA シンポジウム 2001, pp.241-246, Jul 2001. 2001