研究者詳細 - 井上　敏之

論文 - 井上　敏之

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Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier 査読国際誌

A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito, and M. Nakamura

International Conference on Electronics, Information, and Communication (ICEIC) 2022 2022年2月

Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems 査読国際誌

M. Kashiwagi, T. Inoue, M. Okamoto, A. Tsuchiya, and K. Kishine

International Conference on Electronics, Information, and Communication (ICEIC) 2022 2022年2月

A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver 査読国際誌

M. Miyabe, T. Inoue, M. Inoue, S. Nakashioya, A. Tsuchiya, and K. Kishine

2022 International Conference on Electronics, Information, and Communication (ICEIC) 2022年2月

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks 査読国際誌

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) 2021年11月

A method for accelerating the inference process of FPGA-based LSTM for biometric systems 査読国際誌

U. Yoshimura, T. Inoue, A. Tsuchiya, and K. Kishine

IEIE Transactions on Smart Processing and Computing 10 ( 5 ) 416 - 423 2021年10月

Dynamic Memory Access Control for Accelerating FPGA-based Image Processing 査読国際誌

K. Nishiguchi, T. Inoue, R. Yamazaki, K. Ogohara, A. Tsuchiya, and K. Kishine

Journal of Semiconductor Technology and Science 21 ( 1 ) 29 - 38 2021年2月

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS 査読

Ichii Y., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

This paper proposes a 5-Gb/s four-level pulse amplitude modulation (PAM4) transmitter using compensation circuit in data transmission systems. In PAM4 systems, the signal amplitude requires smaller rising and falling times. To achieve this, we adopted an analog feed forward equalizing (FFE) for the compensation in PAM4 transmitter. To confirm the advantage of the proposed technique, we fabricated a 5-Gb/s PAM4 transmitter IC in an 180-nm CMOS process for this work. The measured rising and falling times were 18% and 13% smaller than those without FFE, respectively.

DOI： 10.1109/ICEIC51217.2021.9369819

Scopus

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Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA 査読

Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Regression and classification are necessary for biometric systems and carried out using machine learning. A method for regression and classification is long short-term memory (LSTM). We proposed and implemented algorithms for low-energy LSTM for the regression of microwave-sensor signals into a small-scale FPGA. We found that our FPGA-based parallel (including unrolled)-pipelined algorithm decreased the computation time by 95% compared with the FPGA-based sequential algorithm. In addition, the amount of energy consumption with the proposed algorithm was reduced by 92% and 91% compared with that with a high-end GPU and CPU, respectively.

DOI： 10.1109/ICEIC51217.2021.9369806

Scopus

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Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers 査読

Tanimura S., Tsuchiya A., Inoue T., Kishine K.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 15 - 16 2021年1月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

© 2021 Association for Computing Machinery. This paper presents a supply noise reduction in transimpedance amplifier (TIA) for optical interconnection. TIAs integrated in parallel suffer from inter-channel interference via the supply and the ground lines. We employ an RC filter to reduce the supply noise. The filter is inserted to the first stage of TIA and does not need extra power. The proposed circuit was fabricated in an 180-nm CMOS. The measurement results verify 38% noise reduction at 5 Gbps operation.

DOI： 10.1145/3394885.3431646

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85100590230&origin=inward

Processing Time Reduction for JPEG Compression Using Pixel Array Conversion 査読国際誌

R. Yamazaki, T. Inoue, A. Tsuchiya, and K. Kishine

2020 International SoC Design Conference (ISOCC) 2020年10月

Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking 査読国際誌

A. Tsuchiya, T. Inoue, and K. Kishine

2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) 2020年9月

Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS 査読国際誌

T. Inoue, A. Tsuchiya, and K. Kishine

Journal of Semiconductor Technology and Science 20 ( 2 ) 177 - 186 2020年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Journal of Semiconductor Technology and Science 参加形態：共同（主担当）

© 2020, Institute of Electronics Engineers of Korea. All rights reserved. We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, band-width, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-mm CMOS type.

DOI： 10.5573/JSTS.2020.20.2.177

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85084141823&origin=inward

Capacitive sensor for contact angle estimation of droplet on microfluidic chip 査読国際誌

A. Tsuchiya, T. Inoue, and K. Kishine

2019 IEEE Asia-Pacific Microwave Conference (APMC) 2019年12月

Frequency discriminator using a simple AD converter for interface systems 査読国際誌

S. Kimura, A. Imajo, T. Inoue, A. Tsuchiya, and K. Kishine

2019 International SoC Design Conference (ISOCC) 2019年10月

Optimization technique of memory traffic for FPGA-based image processing system 査読国際誌

K. Nishiguchi, T. Inoue, A. Tsuchiya, K. Ogohara, and K. Kishine

2019 International SoC Design Conference (ISOCC) 2019年10月

Suitable-compensation circuit design for a PAM4 transmitter in 180-nm CMOS 査読国際誌

Y. Ichii, R. Noguchi, T. Inoue, A. Tsuchiya, and K. Kishine

2019 International SoC Design Conference (ISOCC) 2019年10月

Design of crosstalk noise filter for multi-channel transimpedance amplifier 査読国際誌

S. Tanimura, A. Tsuchiya, R. Noguchi, T. Inoue, and K. Kishine

2019 32nd IEEE International System-on-Chip Conference (SOCC) 161 - 164 2019年9月

Impact of on-chip inductor and power-delivery-network stacking on signal and power integrity 査読国際誌

A. Tsuchiya, A. Hiratsuka, T. Inoue, K. Kishine, and H. Onodera

IEICE Transactions on Electronics E102-C ( 7 ) 573 - 579 2019年7月

FPGA-based binary labeling signal transmission system 査読国際誌

T. Inoue, K. Nomura, R. Noguchi, N. Koda, A. Tsuchiya, K. Kishine

Journal of Semiconductor Technology and Science 19 ( 3 ) 276 - 286 2019年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：The Institute of Electronics and Information Engineers 参加形態：共同（主担当）

© 2019, Institute of Electronics Engineers of Korea. All rights reserved. We implemented and evaluated our newly developed binary labeling signal transmission system using field-programmable gate arrays. In this system, the state of “0” or “1” of labeling signals is related to modulation or non-modulation of frame signals, and the labeling signals can be multiplexed to frame signals and transmitted without changing the configuration of the original frame signal. We designed a modulation-system protocol for implementing the above system and propose a digital smoothing technique for stabilizing a phase-locked loop circuit. We verified that our digital smoothing technique prevents bit error of the modulated frame signals in the implemented transmitter. The labeling signal multiplexed to the frame signals is demodulated without bit error in the implemented transceiver.

DOI： 10.5573/JSTS.2019.19.3.276

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85070491085&origin=inward

A 25-Gb/s low-power clock and data recovery with an active-stabilizing CML-CMOS conversion 査読国際誌

R. Noguchi, A. Imajo, T. Inoue, A. Tsuchiya, and K. Kishine

The 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2018) 49 - 52 2018年12月

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