研究者詳細 - 土谷　亮

論文 - 土谷　亮

分割表示 >> ／全件表示174 件中 1 - 174 件目

Cryogenic and RF Modeling of On-Chip Passive Devices for Quantum Computer 招待査読

Akira Tsuchiya

IEEE 17th International Conference on Solid-State and Integrated Circuit Technology 1 - 3 2024年10月

Activities for Open-Source Integrated Circuits Design in Japan 招待査読

Akira Tsuchiya

9th IEEE International Conference on IC Design and Verification 130 - 133 2024年6月

Mean-Free-Path-Based Evaluation of Size Effectand Anomalous Skin Effect in On-Chip Interconnects under Cryogenic Environment 査読

Akira Tsuchiya

28th IEEE Workshop on Signal and Power Integrity 1 - 4 2024年5月

A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks 査読国際誌

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Microelectronics Journal 2024年3月

A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip 査読

T. Inoue, A. Tsuchiya, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura

IEEE Transactions on Circuits and Systems II 2024年

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS 招待査読

2023年10月

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS 査読

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

The 20th International SoC Conference (ISOCC) 2023年10月

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process 査読

Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

IEICE Electronics Express 20 ( 18 ) 2023年9月

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks 査読

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

IEICE Electronics Express 20 ( 14 ) 2023年7月

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS 査読

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura

IEEE International Conference on Electronics, Circuits and Systems (ICECS) 1 - 4 2023年

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS 査読

D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya and K. Kishine

International SoC Design Conference (ISOCC) 13 - 14 2023年

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS 査読国際誌

Inoue T., Tsuchiya A., Kishine K., Ito D., Takahashi Y., Nakamura M.

ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 1 - 4 2022年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 参加形態：共同（副担当）

A burst-mode transimpedance amplifier (TIA) receives burst signals, which are intermittent signals. To reduce the power consumption during the idle times, we propose a burst-mode TIA with automatic power saving in 65-nm CMOS. It enables to provide a stable operation without a DC wander effect while receiving the burst signal. The post-layout simulation results show that the designed TIA can automatically reduce the power consumption during the idle times by 54.2% compared to that during the active times.

DOI： 10.1109/ICECS202256217.2022.9970848

Scopus

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A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band 査読国際誌

Inoue M., Nakashioya S., Inoue T., Tsuchiya A., Kishine K.

ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 1 - 4 2022年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

Recently, radio-wave sensors have been utilized in automotive radar and biological sensing applications. Although beamforming using an array antenna is effective method for changing the radiation directivity, the phase-shift error causes degradation of the directivity significantly. In this paper, we propose a fine-tuning phase shifter with a vector synthesizer, which enables to control the phase-shift amount continuously in 24-GHz band. From the measurement results of the fabricated phase shifter using 65-nm CMOS technology, the variable phase-shift amount over a range of 360◦ is obtained continuously. In addition, the estimated radiation patterns show that the phase-shift and amplitude errors of the fabricated phase shifter are acceptable.

DOI： 10.1109/ICECS202256217.2022.9970921

Scopus

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A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA 査読国際誌

Okamoto M., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 55 - 56 2022年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Proceedings - International SoC Design Conference 2022, ISOCC 2022 参加形態：共同（副担当）

We propose a method for implementing an LSTM-based multiple-people identification system on a small-scale FPGA. To reduce the hardware-resource usage, we introduce a digit adjustment and bit reduction method for converting the floating-point type to the fixed-point type with high precision. It enables not only to reduce the hardware-resource usage without degrading the identification accuracy but also to shorten the computation time by 50% compared to that of the conventional floating-point type.

DOI： 10.1109/ISOCC56007.2022.10031374

Scopus

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Smart Computational Resource Distribution System with Automatic Classification Interface for CPS 査読国際誌

Teramura Y., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 101 - 102 2022年10月

This paper describes a proposal for a classification interface for computational resources distribution in CPS. The classification interface enables to distribute processing to the different computational resources (CPU and FPGA) automatically depending on the type of the processing. As a result, the total processing time is shortened by 50.9% compared to that of the system without the classification interface.

DOI： 10.1109/ISOCC56007.2022.10031427

Scopus

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Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing 査読国際誌

Shimohane S., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 338 - 339 2022年10月

In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAMbased system.

DOI： 10.1109/ISOCC56007.2022.10031293

Scopus

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A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS 査読国際誌

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura

65th IEEE International Midwest Symposium on Circuits and Systems 1 - 4 2022年8月

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad 査読国際誌

A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura

IEEE 65th International Midwest Symposium on Circuits and Systems 1 - 4 2022年8月

Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit 査読

Takahashi Y., Ito D., Namamura M., Tsuchiya A., Inoue T., Kishine K.

Electronics (Switzerland) 11 ( 6 ) 2022年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Electronics (Switzerland)

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dBΩ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 µm × 225 µm.

DOI： 10.3390/electronics11060854

Scopus

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Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion 査読国際誌

Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 579 - 582 2022年2月

A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver 査読国際誌

Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 644 - 647 2022年2月

Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems 査読国際誌

Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 616 - 619 2022年2月

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier 査読国際誌

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, and Makoto Nakamura

International Conference on Electronics, Information, and Communication 640 - 643 2022年2月

Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS 査読国際誌

Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

The 27th Asia and South Pacific Design Automation Conference 96 - 97 2022年1月

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks 査読国際誌

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) 1 - 6 2021年11月

Dynamic Memory Access Control for Accelerating FPGA-based Image Processing 査読国際誌

Kenta Nishiguchi, Toshiyuki Inoue, Rei Yamazaki, Kazunori Ogohara, Akira Tsuchiya, Keiji Kishine

Journal of Semiconductor Technology and Science 21 ( 1 ) 29 - 38 2021年2月

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS 査読

Ichii Y., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

This paper proposes a 5-Gb/s four-level pulse amplitude modulation (PAM4) transmitter using compensation circuit in data transmission systems. In PAM4 systems, the signal amplitude requires smaller rising and falling times. To achieve this, we adopted an analog feed forward equalizing (FFE) for the compensation in PAM4 transmitter. To confirm the advantage of the proposed technique, we fabricated a 5-Gb/s PAM4 transmitter IC in an 180-nm CMOS process for this work. The measured rising and falling times were 18% and 13% smaller than those without FFE, respectively.

DOI： 10.1109/ICEIC51217.2021.9369819

Scopus

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Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA 査読

Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Regression and classification are necessary for biometric systems and carried out using machine learning. A method for regression and classification is long short-term memory (LSTM). We proposed and implemented algorithms for low-energy LSTM for the regression of microwave-sensor signals into a small-scale FPGA. We found that our FPGA-based parallel (including unrolled)-pipelined algorithm decreased the computation time by 95% compared with the FPGA-based sequential algorithm. In addition, the amount of energy consumption with the proposed algorithm was reduced by 92% and 91% compared with that with a high-end GPU and CPU, respectively.

DOI： 10.1109/ICEIC51217.2021.9369806

Scopus

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Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers 査読国際誌

Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

Asia-South Pacific Design Automation Conference 15 - 16 2021年1月

A Method for Accelerating the Inference Process of FPGA-based LSTM for Biometric Systems 査読

Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

IEIE Transactions on Smart Processing and Computing 10 ( 5 ) 416 - 423 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEIE Transactions on Smart Processing and Computing

Biometric systems require the regression and classification of biological sensing data, which are both carried out using machine learning. Long short-term memory (LSTM) is one of the most common methods used for regression and classification. We have developed and implemented a low-energy LSTM algorithm for the regression of microwave sensor signals in a small-scale FPGA. Experimental results show that the FPGA-based parallel-pipelined unrolled algorithm can reduce the computation time by 95% compared to an FPGA-based sequential algorithm. In addition, we found that the power consumption can be reduced by 92% and 91% compared to that obtained with a high-end GPU and CPU, respectively.

DOI： 10.5573/IEIESPC.2021.10.5.416

Scopus

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Processing Time Reduction for JPEG Compression Using Pixel Array Conversion 査読国際誌

Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

17th International SoC Design Conference 2020年10月

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS 査読国際誌

Akira TSUCHIYA, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, Hidetoshi ONODERA

IEiCE Transactions on Electronics E103-C ( 10 ) 489 - 496 2020年10月

Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking 招待査読国際誌

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

2020 IEEE International Symposium on Radio-Frequency Integration Technology 12 - 14 2020年9月

Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS 査読

Inoue T., Tsuchiya A., Kishine K.

Journal of Semiconductor Technology and Science 20 ( 2 ) 177 - 186 2020年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Journal of Semiconductor Technology and Science 参加形態：共同（副担当）

© 2020, Institute of Electronics Engineers of Korea. All rights reserved. We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, band-width, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-mm CMOS type.

DOI： 10.5573/JSTS.2020.20.2.177

Scopus

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Capacitive Sensor for Contact Angle Estimation of Droplet on Microfluidic Chip 査読国際誌

Akira Tsuchiya, Toshiyuki Inoue and Keiji Kishine

2019 Asia-Pacific Microwave Conference 2019年12月

Frequency Discriminator Using a Simple AD Converter for Interface Systems 査読国際誌

Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

16th International SoC Design Conference 2019年10月

Optimization Technique of Memory Traffic for FPGA-Based Image Processing System 査読国際誌

Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara and Keiji Kishine

16th International SoC Design Conference 2019年10月

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS 査読国際誌

Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

16th International SoC Design Conference 2019年10月

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS 査読国際誌

Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

32nd International System-on-Chip Conference 2019年9月

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier 査読国際誌

Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine

32nd IEEE International System-on-Chip Conference 2019年9月

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity 査読

Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA

IEICE TRANSACTIONS on Electronics E102-C ( 7 ) 573 - 579 2019年7月

FPGA-based binary labeling signal transmission system 査読

Inoue T., Nomura K., Noguchi R., Koda N., Tsuchiya A., Kishine K.

Journal of Semiconductor Technology and Science 19 ( 3 ) 276 - 286 2019年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Journal of Semiconductor Technology and Science

© 2019, Institute of Electronics Engineers of Korea. All rights reserved. We implemented and evaluated our newly developed binary labeling signal transmission system using field-programmable gate arrays. In this system, the state of “0” or “1” of labeling signals is related to modulation or non-modulation of frame signals, and the labeling signals can be multiplexed to frame signals and transmitted without changing the configuration of the original frame signal. We designed a modulation-system protocol for implementing the above system and propose a digital smoothing technique for stabilizing a phase-locked loop circuit. We verified that our digital smoothing technique prevents bit error of the modulated frame signals in the implemented transmitter. The labeling signal multiplexed to the frame signals is demodulated without bit error in the implemented transceiver.

DOI： 10.5573/JSTS.2019.19.3.276

Scopus

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A 25-Gb/s Low-Power Clock and Data Recovery with an ActiveStabilizing CML-CMOS Conversion 査読国際誌

Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

The 25th IEEE International Conference on Electronics Circuits and Systems 2018年12月

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-less Bandwidth Compensation 査読国際誌

Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

IEEE Asian Solid-State Circuits Conference 69 - 72 2018年11月

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback 査読国際誌

Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, and Hidetoshi Onodera

The 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2018) 2018年8月

Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net 査読国際誌

Akira TSUCHIYA, Akitaka HIRATSUKA, Toshiyuki INOUE, Keiji KISHINE, Hidetoshi ONODERA

IEEE Workshop on Signal and Power Integrity 1 - 4 2018年5月

A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS 査読国際誌

Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka

International Symposia on VLSI Design, Automation and Test 2018年4月

Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS 査読国際誌

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura

International SoC Design Conference 2017年11月

FPGA-Based Transceiver Circuit for Labeling Signal Transmission System 査読国際誌

Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

International SoC Design Conference 2017年11月

Compact Implementation IIR Filter in FPGA for Noise Reduction of Sensor Signal 査読国際誌

Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

International SoC Design Conference 2017年11月

Power-Bandwidth Trade-Off Analysis of Multi-Stage Inverter-Type Transimpedance Amplifier for Optical Communication 査読国際誌

Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera

MWSCAS2017 2017年8月

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS 査読国際誌

T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto

IEIE Transactions on Smart Signal and Computing 5 ( 3 ) 207 - 214 2016年6月

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS 査読

T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto

IEIE Transactions on Smart Signal and Computing 5 ( 3 ) 207 - 214 2016年6月

A 32-Gb/s output buffer circuit with doubled pre-emphasis in 65-nm CMOS 査読

International Conference on Electronics, Information, and Communication 2016年1月

A 25-Gb/s 480-mW CMOS Modulator Driver Using Area-Efficient 3D Inductor Peaking 査読

IEEE Asian Solid-State Circuits Conference 2015年11月

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage 査読

N. Kamae, A. Tsuchiya, H. Onodera

IEICE Transactions on Electronics 98-C ( 6 ) 504 - 511 2015年6月

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage 査読

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS E98C ( 6 ) 504 - 511 2015年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5V to 1.2V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65 nm CMOS process. Area of the AES core is 0 : 22 mm(2) and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5V to 1.2V which enables the reduction of power dissipation, for example, of 17% at 400MHz operation.

DOI： 10.1587/transele.E98.C.504

Web of Science

Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 査読

K. Kishine, H. Inaba, H. Inoue, M. Nakamura, A. Tsuchiya, H. Katsurai, H. Onodera

IEEE Transactions on Circuits and Systems I 62 ( 5 ) 1288 - 1295 2015年5月

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 査読

Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 62 ( 5 ) 1288 - 1295 2015年5月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

A multi-rate burst-mode clock and data recovery ( BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW.

DOI： 10.1109/TCSI.2015.2416812

Web of Science

A wireless neural recording system with a precision motorized microdrive for freely behaving animals 査読国際誌

T. Hasegawa, H. Fujimoto, K. Tashiro, M. Nonomura, A. Tsuchiya, D. Watanabe

Scientific Reports 5 ( 7853 ) 2015年1月

A wireless neural recording system with a precision motorized microdrive for freely behaving animals 査読

Taku Hasegawa, Hisataka Fujimoto, Koichiro Tashiro, Mayu Nonomura, Akira Tsuchiya, Dai Watanabe

SCIENTIFIC REPORTS 5 7853 2015年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：NATURE PUBLISHING GROUP

The brain is composed of many different types of neurons. Therefore, analysis of brain activity with single-cell resolution could provide fundamental insights into brain mechanisms. However, the electrical signal of an individual neuron is very small, and precise isolation of single neuronal activity from moving subjects is still challenging. To measure single-unit signals in actively behaving states, establishment of technologies that enable fine control of electrode positioning and strict spike sorting is essential. To further apply such a single-cell recording approach to small brain areas in naturally behaving animals in large spaces or during social interaction, we developed a compact wireless recording system with a motorized microdrive. Wireless control of electrode placement facilitates the exploration of single neuronal activity without affecting animal behaviors. Because the system is equipped with a newly developed data-encoding program, the recorded data are readily compressed almost to theoretical limits and securely transmitted to a host computer. Brain activity can thereby be stably monitored in real time and further analyzed using online or offline spike sorting. Our wireless recording approach using a precision motorized microdrive will become a powerful tool for studying brain mechanisms underlying natural or social behaviors.

DOI： 10.1038/srep07853

Web of Science

Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation 査読

Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) 181 - 185 2015年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

Energy-efficiency has become the driving force of today's LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.

DOI： 10.1109/ISQED.2015.7085421

Web of Science

PLL の物理レイアウト自動生成を目指した設計手法査読

釡江典裕, 土谷亮, 石原亨, 小野寺秀俊

情報処理学会DA シンポジウム 2014年8月

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure 査読

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS E97C ( 4 ) 325 - 331 2014年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a radiation-hardened phase-locked loop (RH-PLL) with a switchable dual modular redundancy (DMR) structure. After radiation strikes, unhardened PLLs suffer clock perturbations. Conventional RH-PLLs have been proposed to reduce recovery time after perturbation. However, this recovery still requires tens of clock cycles. Our proposal involves 'detecting' and 'switching', rather than 'recovering' from clock perturbation. Detection speed is crucial for robust perturbation-immunity. We identify types of clock perturbation and then propose a set of detectors to detect each type. With this method, the detectors guarantee high-speed detection that leads to perturbation-immune switching from a radiated clock to an undistorted clock. The proposed RH-PLL was fabricated and then verified with a radiation test on real silicon.

DOI： 10.1587/transele.E97.C.325

Web of Science

Analysis of radiation-induced clock-perturbation in phase-locked Loop 査読

S.N. Kim, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 3 ) 768 - 776 2014年3月

A body bias generator with low supply voltage for within-die variability compensation 査読

N. Kamae, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 3 ) 734 - 740 2014年3月

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation 査読

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 3 ) 734 - 740 2014年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and Power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6 V to 1.2 V. We fabricated the BBG in a 65 nm CMOS process to control 0.1 mm(2) of core circuit with the area overhead of 1.4% for the BBG.

DOI： 10.1587/transfun.E97.A.734

Web of Science

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop 査読

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 3 ) 768 - 776 2014年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper presents an analysis of radiation-induced clock-perturbation in phase-locked loop (PLL). Due to a trade-off between cost, performance, and reliability, radiation hardened PLL design need robust strategy. Thus, evaluation of radiation vulnerability is important to choose the robust strategy. The conventional evaluation-method is however based on brute-force analysis - SPICE simulation and experiment. The presented analysis result eliminates the brute-force analysis in evaluation of the radiation vulnerability. A set of equations enables to predict the radiation-induced clock-perturbation at the every sub-circuits. From a demonstration, the most vulnerable nodes have been found, which are validated using a PLL fabricated with 0.18 mu m CMOS process.

DOI： 10.1587/transfun.E97.A.768

Web of Science

Radiation-hardened PLL with a switchable dual modular redundancy structure 査読

S.N. Kim, A. Tsuchiya, H. Onodera

IEICE Transactions on Electronics E97-C ( 4 ) 325 - 331 2014年1月

25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS 査読

Tomoki Tanaka, Keiji Kishine, Hiromi Inaba, Akira Tsuchiya

2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 94 - 95 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A 25-Gb/s inductorless output buffer circuit with a pre-emphasis is proposed. We designed the circuit parameters according to the frequency characteristics of the emphasized signal. To confirm the advantages of the emphasis circuit, we fabricated an output buffer IC in a 65-nm CMOS process. The proposed circuit has a control voltage to adjust the emphasis amplitude according to the load outside the chip. Measurement results showed that the jitters were 40% lower with the emphasis circuit than without, indicating that our proposed configuration can be applied to the design of output buffer circuits for higher operation speed.

DOI： 10.1109/ISOCC.2014.7087578

Web of Science

A Body Bias Generator with Wide Supply-Range down to Threshold Voltage for Within-Die Variability Compensation 査読

Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Hidetoshi Onodera

2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) 53 - 56 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. While FGBB is effective in reducing variability and power consumption, a number of BBGs are required on a die and therefore simplified design of BBGs is necessary. This paper proposes a cell-based design of a BBG that generates forward and reverse body bias voltages only from a core supply voltage ranging from the near threshold of 500mV to the nominal voltage of 1.2V. This wide operating range is achieved by a low voltage error amplifier with a V-th biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm low power CMOS process to control 0.22mm(2) of core circuit with the area overhead of 2.3% for the BBG.

DOI： 10.1109/ASSCC.2014.7008858

Web of Science

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops 査読

Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 2704 - 2707 2014年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A 12.5-Gb/s burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops which operate complementarily. The same type of circuit configurations are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a 12.5-Gb/s-BCDR IC with the 65-nm-MOSFET process. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gis. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW, respectively.

DOI： 10.1109/ISCAS.2014.6865731

Web of Science

\Analysis of Radiation-Induced Timing Vulnerability on Phase- locked Loops 査読

S.N. Kim, A. Tsuchiya, H. Onodera

情報処理学会DA シンポジウム 2013年8月

A 25-Gb/s LD Driver with Area-Effective Inductor in a 0.18-mu m CMOS 査読

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 105 - 106 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper presents high-speed and area-efficient laser-diode driver with interwoven inductor in a 0.18-mu m CMOS. We interweave ten peaking inductors for area-effective implementation as well as performance enhancement. Interwoven inductor can not only achieve area-efficiency but also tune frequency characteristic. Mutual inductances of interwoven inductor enhance bandwidth and suppress group delay dispersion. The test chip area is 0.32 mm(2) and the maximum operating speed is 25 Gb/s.

DOI： 10.1109/ASPDAC.2013.6509578

Web of Science

Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits 査読

Akira Tsuchiya, Hidetoshi Onodera

IMFEDK 2013 - 2013 International Meeting for Future of Electron Devices, Kansai 106 - 107 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper discusses loss of on-chip transmission-line in terahertz region. Above 100 GHz, modeling of on-chip transmission-line is an important issue. We evaluate the impact of eddy current and anomalous skin effect by a field solver. Simulation results show that eddy current in dummy fills has higher impact of 10% on transmission-line loss. Anomalous skin effect is not negligible, but its impact is about 5% at 100 GHz. © 2013 IEEE.

DOI： 10.1109/IMFEDK.2013.6602261

Scopus

Advanced RF and analog integrated circuits for fourth generation wireless communications and beyond 査読

Ramesh Pokharel, Leonid Belostotski, Akira Tsuchiya, Ahmed Allam, Mohammad S. Hashmi

International Journal of Microwave Science and Technology 2013年

A slow-wave transmission line with thin pillars for millimeter-wave CMOS 査読

Taro Amagai, Akira Tsuchiya, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera

2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper presents a slow-wave transmission line with thin pillars on strips shield. Slow-wave transmission lines are mostly used as stub filters. The proposed structure with pillars has higher capacitance and inductance per unit length of the line. Thus, high phase constant and quality factor can be achieved. We compare simulation results between the proposed structure and conventional lines for millimeter-wave CMOS. The proposed line gives higher phase constant of 3.1 rad/mm and high quality factor of 21.6 at 60 GHz. © 2013 IEEE.

DOI： 10.1109/SaPIW.2013.6558341

Scopus

Perturbation-immune radiation-hardened PLL with a switchable DMR structure 査読

Sin Nyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013 128 - 132 2013年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper proposes a perturbation-immune radiation-hardened PLL with a switchable dual modular redundancy (DMR) structure. By a radiation-strike, a PLL has clock-perturbation for a while. Conventional RHPLLs are proposed to reduce recovery-time which is the time to recover from perturbation. However, recovery still needs tens of clock cycles. Our proposal is 'detecting' and 'switching' instead of 'recovering' clock-perturbation. For robust perturbation-immunity, detecting speed is important. We identify types of clock-perturbation and-then propose a set of detectors to detect each type. With this, detectors guarantee high speed in detection. © 2013 IEEE.

DOI： 10.1109/IOLTS.2013.6604063

Scopus

Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation 査読国際誌

A. K. M. Mahfuzul Islam, A. Tsuchiya, K. Kobayashi, H. Onodera

IEEE Transactions on Semiconductor Manufacturing 25 ( 4 ) 571 - 580 2012年11月

A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation 査読

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEEE Asian Solid-State Circuits Conference(A-SSCC) 2012, pp. 389-392, Nov 2012. 2012年11月

Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation 査読

Islam A. K. M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 25 ( 4 ) 571 - 580 2012年11月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation.

DOI： 10.1109/TSM.2012.2198677

Web of Science

Dual-PLL based on Temporal Redundancy for Radiation-Hardening 査読

SinNyoung KIM, Akira TSUCHIYA, Hidetoshi ONODERA

Proceedings of 10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications 2012年10月

Modeling of Single-Event Failures in Dividerand PFD of PLLs based on Jitter Analysis 査読

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

13th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2012. 2012年9月

チップ内基板バイアス生成回路のモジュール化設計査読

釡江典裕, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム2012論文集, pp. 55-60, Aug 2012. 2012年8月

Area-effective inductive peaking with interwoven inductor for high-speed laser-diode driver for optical communication system 査読

T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95-A ( 2 ) 479 - 486 2012年2月

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System 査読

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 2 ) 479 - 486 2012年2月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 mu m CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

DOI： 10.1587/transfun.E95.A.479

Web of Science

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18μm CMOS 査読

T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 561 - 562 2012年

Impact of radiation loss in on-chip transmission-line for terahertz applications 査読

Akira Tsuchiya, Hidetoshi Onodera

2012 IEEE 16th Workshop on Signal and Power Integrity, SPI 2012 - Proceedings 125 - 128 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper discusses radiation loss of on-chip transmission-line. Since terahertz applications of integrated circuits are emerging, precise modeling in terahertz region is needed. We evaluate conductor loss, dielectric loss and radiation loss of on-chip transmission-line by a full-wave field solver. Simulation results show that design focusing conductor loss may cause large radiation loss in terahertz region. Quantitative evaluation of the impact of radiation loss is demonstrated. Also we show that thick signal wire and differential line is effective to reduce the loss. © 2012 IEEE.

DOI： 10.1109/SaPIW.2012.6222926

Scopus

A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μm CMOS 査読

S. Miyawaki, M. Nakamura, A. Tsuchiya, K. Kishine, H. Onodera

2011 International SoC Design Conference, ISOCC 2011 223 - 226 2011年

Gradient Resistivity Method for Numerical Evaluation of Anomalous Skin Effect 査読

Akira Tsuchiya, Hidetoshi Onodera

2011 15TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS (SPI) 139 - 142 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper discusses a method to evaluate anomalous skin effect. Anomalous skin effect (ASE) is a phenomenon which appears when the skin depth becomes comparable to the mean free path of electrons. In anomalous region, the effective resistivity depends on skin depth. Thus it is difficult to evaluate by field-solvers. The proposed method realizes field simulation considering ASE by gradient resistivity. Simulation result shows that the resistance increase more rapid than classical skin effect above 100GHz. The effect on the resistance is 5% at 100GHz and 10% at 300GHz.

DOI： 10.1109/SPI.2011.5898859

Web of Science

An area effective forward/reverse body bias generator for within-die variability compensation 査読

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011 217 - 220 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To compensate the die-to-die and location correlated variation, we propose to split digital circuit to sub-mm-scale area controlling each area with an on-chip forward/reverse body bias generator (BBG). The proposed BBG is configured as a feedforward control system to achieve small area. The BBG is realized by combining a low output resistance DAC and a charge pump type level shifter. The BBG design is implemented with 1.2V thin gate oxide MOSFET in a 65nm CMOS technology. The simulation and measurement results show that the variation is compensated with an area overhead as small as 2%. © 2011 IEEE.

DOI： 10.1109/ASSCC.2011.6123641

Scopus

Variation-sensitive monitor circuits for estimation of die-to-die process variation 査読

I.A.K.M. Mahfuzul, A. Tsuchiya, K. Kobayashi, H. Onodera

IEEE International Conference on Microelectronic Test Structures 153 - 157 2011年

レイアウト制約が性能と製造性に与える影響査読

北島和彦, 砂川洋輝, 土谷亮, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2010 ( 7 ) 221 - 226 2010年8月

Effect of regularity-enhanced layout on variability and circuit performance of standard cells 査読

H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, H. Onodera

IPSJ Transactions on System LSI Design Methodology 3 130 - 139 2010年2月

A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18-mu m CMOS 査読

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A laser-diode (LD) driver with interwoven mutually-coupled peaking inductors for high-speed optical networks is presented. Six and four inductors are interwoven into two sets of inductors for area-effective implementation as well as performance enhancement. The proposed circuit is fabricated in CMOS 0.18-mu m process. The circuit area is 0.34mm(2) and the maximum operating speed is 16Gbps. Compared to a conventional LD driver in 0.18-mu m CMOS, the proposed circuit achieves 1.6 times faster operation, 26% smaller area with 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current.

DOI： 10.1109/CICC.2010.5617416

Web of Science

Measurement of on-chip transmission-line with stacked split-ring resonators 査読

Akira Tsuchiya, Hidetoshi Onodera

2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings 137 - 140 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper reports measurement results of on-chip transmission-line with split-ring resonators. Split-ring resonator (SRR) has attracted attention as an implementation of metamaterial (left-handed material). However when simple SRR is implemented in LSIs, the resonance frequency becomes around 200GHz and it is too high to employ on on-chip circuits. We designed a stacked SRR to lower the resonant frequency in a 0.18//m CMOS. Measurement results show that the stacked SRRs can realize the resonance frequency below 50GHz. Also measurement results show a guideline of area effective implementation of on-chip SRR. © 2010 IEEE.

DOI： 10.1109/SPI.2010.5483544

Scopus

Effect of regularity-enhanced layout on variability and circuit performance of standard cells 査読

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IPSJ Transactions on System LSI Design Methodology 3 130 - 139 2010年

記述言語：英語掲載種別：研究論文（学術雑誌）

As the minimum feature size shrinks down far below sub-wavelength, Design for Manufacturability or layout regularity plays an important role for maintaining pattern fidelity in photolithography. However, it also incurs overheads in circuit performances due to parasitic capacitance. In this paper, we examine the effect of layout regularity on printability and circuit performance by lithography simulation and transistor-level simulation. It is shown that regularity-enhanced cells provide better Critical Dimension (CD) stability under defocus and lead to delay increase. Then we evaluate the effect of layout regularity by a real chip measurement in 90 nm, 65 nm and 45 nm processes. For example, in a 65 nm process, inverter Ring Oscillators (ROs) that have the smallest poly pitch with dummy-poly insertion exhibits 19% reduction of WID and D2D variation with delay overhead of 2.5%, compared to the ROs without dummy-poly insertion. However, we have observed that the effect of layout regularity varies depending on fabrication processes and circuit structures. It is therefore important to obtain the best trade-off among performance overhead and variability reduction for each process technology. © 2010 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.3.130

Scopus

A design procedure of predictive RF MOSFET model for compatibility with ITRS 査読

Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings - IEEE International SOC Conference, SOCC 2010 396 - 399 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

A design procedure for generating predictive MOS-FET models is proposed. Due to evolving nature of future prediction, predictive models based on a certain prediction soon become absolute. We have therefore developed a design procedure for maintaining compatibility with most up-to-date prediction such as ITRS. The design procedure can generate predictive RF models for the first time. Details of the design procedure for BSIM4 as a core model are explained, with an application to LNA design example. © 2010 IEEE.

DOI： 10.1109/SOCC.2010.5784704

Scopus

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-μm CMOS 査読

T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

Proceedings of the Custom Integrated Circuits Conference 2010年

Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability 査読

A.K.M Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

Tau Workshop 2010, Mar 2010. 2010年

Statistical gate delay model for multiple input switching 査読

T. Fukuoka, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 12 ) 3070 - 3078 2009年12月

Statistical Gate Delay Model for Multiple Input Switching 査読

Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3070 - 3078 2009年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the Output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80% error in worst case. The error of the proposed method is less than 20%.

DOI： 10.1587/transfun.E92.A.3070

Web of Science

チップ内ばらつきが順序セルの動作特性に与える影響査読

砂川洋輝, 土谷亮, 小林和淑, 小野寺秀俊

情報処理学会DA シンポジウム 2009年8月

Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells 査読

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2 195 - 200 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-off among manufacturability, cost, and performance for each process technology. This paper discusses the efiect of layout regularity on printability and circuit performance in 90 45nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows in a 45nm process. We demonstrate the quantitative evaluation of the trade-off between printability and circuit performance of regularity-enhanced standard cells.

DOI： 10.1109/ISQED.2009.4810293

Web of Science

On-Chip Metamaterial Transmission-Line Based on Stacked Split-Ring Resonator for Millimeter-Wave LSIs 査読

Akira Tsuchiya, Hidetoshi Onodera

APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 1458 - 1461 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a method to realize on-chip metamaterial transmission-line. Since the resonant frequency of split-ring resonator (SRR) depends on the size strongly, it is difficult to realize metamaterial transmission-line in integrated circuits. If we implement a conventional SRR to on-chip transmission-line, the resonant frequency is around 200GHz. We propose a stacked SRR using on-chip multi-layer interconnect. The stacked SRR is evaluated by a field-solver and the experimental results verify that the stacked SRR can realize the resonant frequency below 60GHz.

DOI： 10.1109/APMC.2009.5384480

Web of Science

High performance on-chip differential signaling using passive compensation for global communication 査読

L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E.S. Kuh, C.-K. Cheng

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 385 - 390 2009年

Effect of underlayer dummy fills on on-chip transmission line 査読

A. Tsuchiya, H. Onodera

2009 IEEE Workshop on Signal Propagation on Interconnects, SPI \\'09 2009年

Analytical eye-diagram model for on-chip distortionless transmission lines and its application to design space exploration 査読

M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A ( 12 ) 3474 - 3480 2008年12月

Patterned floating dummy fill for on-chip spiral inductor considering the effect of dummy fill 査読国際誌

A. Tsuchiya, H. Onodera

IEEE Transactions on Microwave Theory and Techniques 56 ( 12 ) 3217 - 3222 2008年12月

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration 査読

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 12 ) 3474 - 3480 2008年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.

DOI： 10.1093/ietfec/e91-a.12.3474

Web of Science

Patterned Floating Dummy Fill for On-Chip Spiral Inductor Considering the Effect of Dummy Fill 査読

Akira Tsuchiya, Hidetoshi Onodera

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 56 ( 12 ) 3217 - 3222 2008年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper discusses the effect of dummy fills on the performance of spiral inductors. In Si-CMOS processes that use copper wire, metal dummy fills are required to prevent thickness fluctuation in the chemical mechanical polishing stage. Dummy fills have been thought to affect the wire capacitance; however, in high frequency, dummy fills also affect the wire resistance and the wire inductance due to the eddy current in dummy fills. This work evaluates the effect of the dummy fills by three-dimensional field solver and proposes a structure to suppress the effect of dummy fills. Experimental results show that the proposed method can decrease the effect of dummy fills on the Q-factor by 83% compared with the conventional dummy fill insertion.

DOI： 10.1109/TMTT.2008.2007362

Web of Science

Accurate estimation of the worst-case delay in statistical static timing analysis 査読

H. Terada, T. Fukuoka, A. Tsuchiya, H. Onodera

IPSJ Transactions on System LSI Design Methodology 1 116 - 125 2008年8月

Accurate estimation of the worst-case delay in statistical static timing analysis 査読

Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IPSJ Transactions on System LSI Design Methodology 1 116 - 125 2008年8月

記述言語：英語掲載種別：研究論文（学術雑誌）

In this paper, we propose an approximation method for the statistical MAX operation such that it results in a normal distribution good for the worst-case delay analysis. The important operation in SSTA is SUM and MAX of distributions. In general, the delay variation is modeled as normal distribution. The result of SUM operation of two normal distributions is also normal distribution. On the other hand, the result of MAX operation is not normal distribution. Thus approximation to normal distribution is commonly used. We also explain that the proposed MAX operation at each gate also contributes to the accurate estimation in the worst-case delay analysis of the whole circuit. Experimental results show that the proposed method leads to a good approximation for a normal distribution resulted from MAX operation of normal distributions with and without correlation, and the approximation improves the accuracy of the worst-case delay analysis. In a circuit example, the errors of worst-case delay computed by the previous method are about 20%, and the errors computed by the proposed method are under 5%. © 2008 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.1.116

Scopus

リングオシレータアレイによるゲート遅延ばらつきの評価とモデル化査読

寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2008 ( 7 ) 199 - 204 2008年8月

レイアウト規則性が回路性能とばらつきに及ぼす影響の評価査読

砂川洋輝, 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2008 ( 7 ) 67 - 72 2008年8月

Dummy fill insertion considering the effect on high-frequency characteristics of spiral inductors 査読

A. Tsuchiya, H. Onodera

IEEE MTT-S International Microwave Symposium Digest 787 - 790 2008年

On-chip high performance signaling using passive compensation 査読

Z. Yulei, Z. Ling, A. Tsuchiya, M. Hashimoto, C.-K. Cheng

26th IEEE International Conference on Computer Design 2008, ICCD 182 - 187 2008年

Statistical gate delay model for multiple input switching 査読

T. Fukuoka, A. Tsuchiya, H. Onodera

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 286 - 291 2008年

同時スイッチングを考慮した統計的遅延解析査読

福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2007 ( 7 ) 13 - 18 2007年8月

統計的遅延解析における遅延分布間の最大値計算手法査読

寺田晴彦, 福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2007 ( 7 ) 7 - 12 2007年8月

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Electronics E90-C ( 6 ) 1267 - 1273 2007年6月

Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver 査読

T. Kuboki, A. Tsuchiya, H. Onodera

IEICE Transactions on Electronics E90-C ( 6 ) 1274 - 1281 2007年6月

Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver 査読

Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS E90C ( 6 ) 1274 - 1281 2007年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip trans mission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

DOI： 10.1093/ietele/e90-c.6.1274

Web of Science

ダミーフィルがオンチップ配線の高周波特性に与える影響の解析的評価手法 (第20回回路とシステム軽井沢ワークショップ論文集) -- (デバイスモデリング) 査読

土谷亮, 小野寺秀俊

回路とシステム軽井沢ワークショップ論文集 20 19 - 22 2007年4月

A 10Gbps/channel on-chip signaling circuit with an impedance-unmatched CML driver in 90nm CMOS technology 査読

T. Kuboki, A. Tsuchiya, H. Onodera

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 120 - 121 2007年

Measurement of interconnect loss due to dummy fills 査読

Akira Tsuchiya, Hidetoshi Onodera

2007 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS 241 - 244 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper reports measurement results of on-chip interconnects with CMP dummy fill. CMP dummy fill is a floating metal for metal density adjustment. In high frequency above 10GHz, the eddy current induced in dummy fills affects the interconnect loss. We fabricated test structures of on-chip interconnect with dummy fills. From the measurement results, the effect of the dummy fills on the wire resistance is not negligible even if the ground wires are adjacent to the signal wire. The dummy fills in the upper/lower metal layer affect the wire resistance and the resistance increases by 20% at 50GHz.

DOI： 10.1109/SPI.2007.4512261

Web of Science

Effect of dummy fills on high-frequency characteristics of on-chip interconnects 査読

Akira Tsuchiya, Hidetoshi Onodera

Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006 275 - 278 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper discusses the effect of dummy fills on on-chip interconnect characteristics. The effect of dummy fills has been discussed from the viewpoint of the capacitance. However in high frequency, the magnetic coupling between the signal current and the eddy current in the dummy fills is not negligible. We evaluate the characteristics of on-chip interconnects with dummy fills by a 3D field solver. The size and the location of dummy fills are varied. We also evaluate the effect of dummy fills in the other interconnect layers. Experimental results shows that the impact of the dummy fills on the resistance and the attenuation is not negligible in high frequency such as 50GHz, and the dummy fills in the other layers have strong effect to the interconnect characteristics. The increase of the attenuation constant due to the dummy fills becomes 20% in maximum. ©2006 IEEE.

DOI： 10.1109/SPI.2006.289243

Scopus

Effect of Dummy Fills on High frequency characteristics of Spiral Inductor 査読

Akira Tsuchiya, Hidetoshi Onodera

14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007), pp.256-260, Oct 2007. 2007年

Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration 査読

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 869 - 872 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Institute of Electrical and Electronics Engineers Inc.

DOI： 10.1109/CICC.2007.4405866

Scopus

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design 査読

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006 227 - 230 2007年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

DOI： 10.1109/SPI.2006.289229

Web of Science

Worst-case delay analysis considering the variability of transistors and interconnects 査読

T. Fukuoka, A. Tsuchiya, H. Onodera

Proceedings of the International Symposium on Physical Design 35 - 42 2007年

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design 査読

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 12 ) 3560 - 3568 2006年12月

Interconnect RL extraction based on transfer characteristics of transmission-line 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 12 ) 3585 - 3593 2006年12月

Interconnect RL extraction based on transfer characteristics of transmission-line 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3585 - 3593 2006年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. Experimental results show that the proposed method provides accurate transition waveforms over various interconnect topologies.

DOI： 10.1093/ietfec/e89-a.12.3585

Web of Science

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design 査読

Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3560 - 3568 2006年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

DOI： 10.1093/ietfec/e89-a.12.3560

Web of Science

トランジスタと配線構造のばらつきを考慮した遅延時間のワーストケース解析査読

福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2006 ( 7 ) 13 - 18 2006年7月

オンチップ長距離高速信号伝送の性能予測 (信号伝送回路) 査読

土谷亮, 小野寺秀俊

回路とシステム軽井沢ワークショップ論文集 19 393 - 398 2006年4月

出力インピーダンスの調整による高速信号伝送用CMLドライバの低消費電力設計 (信号伝送回路) 査読

久保木猛, 土谷亮, 小野寺秀俊

回路とシステム軽井沢ワークショップ論文集 19 387 - 392 2006年4月

Alternate self-shielding for high-speed and reliable on-chip global interconnect 査読

Y. Yuyama, A. Tsuchiya, K. Kobayashi, H. Onodera

IEICE Transactions on Electronics E89-C ( 3 ) 327 - 333 2006年3月

Alternate self-shielding for high-speed and reliable on-chip global interconnect 査読

Y Yuyama, A Tsuchiya, K Kobayashi, H Onodera

IEICE TRANSACTIONS ON ELECTRONICS E89C ( 3 ) 327 - 333 2006年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.

DOI： 10.1093/ietele/e89-c.3.327

Web of Science

Analytical estimation of interconnect loss due to dummy fills 査読

A. Tsuchiya, H. Onodera

Electrical Performance of Electronic Packaging, EPEP 149 - 152 2006年

Low-Power Design of CML Drivers for On-Chip Transmission-Lines 査読

Akira Tsuchiya, Takeshi Kuboki, Hidetoshi Onodera

SASIMI2006,pp. 177-182 2006年

Interconnect RL extraction at a single representative frequency 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 515 - 520 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. We experimentally verify that the proposed method provides accurate transition waveforms over various interconnect topologies.

Web of Science

Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction 査読

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

International Workshop on Compact Modeling, pp. 51-56, 2006. 2006年

A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection

Akira Tsuchiya

2005年11月

A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection 査読

Kyoto University 2005年11月

CMLを用いたオンチップ長距離高速信号伝送技術の開発

土谷亮, 新名亮規, 橋本昌宜, 小野寺秀俊

第9回システムLSIワークショップ, pp.275--278, Nov 2005. 2005年11月

Performance Limitation of On-chip Global Interconnects for High-speed Signaling 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 4 ) 885 - 891 2005年4月

Design guideline for resistive termination of on-chip high-speed interconnects 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

Proceedings of the Custom Integrated Circuits Conference 2005 608 - 611 2005年

Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005. 2005年

Performance prediction of on-chip high-throughput global signaling 査読

Masanori Hashimoto, Akira Tsuchiya, Akinori Shinmyo, Hidetoshi Onodera

IEEE Topical Meeting on Electrical Performance of Electronic Packaging 2005 79 - 82 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

On-chip global signaling whose performance improves with technology advance is eagerly demanded. This work focuses on wave pipelining on on-chip transmission lines, which is one of probable solutions, and predicts the trend of signaling performance in the future. Experiments reveal that transmission capacity per channel will improve till at least 35nm technology in 10mm-long or below signaling. We also demonstrate that current-mode differential signaling is robust against power supply noise, but power delivery with non-zero impedance degrades the performance. © 2005 IEEE.

DOI： 10.1109/EPEP.2005.1563706

Scopus

配線の伝達特性に基づく抽出周波数決定手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

DAシンポジウム 2005, pp.169-174, Aug 2005. 2005年

オンチップ高速信号伝送における終端抵抗決定手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

第18回回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005. 2005年

Substrate loss of on-chip transmission-lines with power/ground wires in lower layer 査読

A Tsuchiya, M Hashimoto, H Onodera

SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS 2005 201 - 202 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper discusses shielding effect of power/ground wires in lower layer. A conducting substrate affects characteristics of on-chip transmission line. However in many cases on actual chips, there are P/G wires between the signal wire and the substrate that may shield the substrate coupling. We show measurement and simulation results of on-chip transmission-lines with narrow yet many power/ground wires in a lower layer. Experimental results show that narrow power/ground wires in a lower layer in parallel to the signal wire, which are common in LSI power distribution network, shield substrate coupling and suppress substrate loss. On the other hand, orthogonal power/ground wires in a lower layer hardly mitigate substrate coupling.

DOI： 10.1109/SPI.2005.1500944

Web of Science

Return path selection for loop RL extraction 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 2 1078 - 1081 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper propose a systematic method to select power/ground wires that should be considered in interconnect R-L extraction. The return current distribution affects loop characteristic of interconnects. To extract exact RL value, all of return paths have to be considered. However it is impossible because there are huge number of P/G wires in LSIs. As more wires are considered, the extraction accuracy improves but the extraction cost increases undesirably. The proposed method focuses the energy dissipated at P/G wires and utilizes it for screening return paths. Experimental results reveal that our method enables accurate and computationally efficient RL extraction with considering return current distribution.

Web of Science

On-chip global signaling by wave pipelining 査読

M Hashimoto, A Tsuchiya, H Onodera

ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING 311 - 314 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.

Web of Science

Performance limitation of on-chip global interconnects for high-speed signaling 査読

A. Tsuchiya, Y. Gotoh, M. Hashimoto, H. Onodera

Proceedings of the Custom Integrated Circuits Conference 489 - 492 2004年

Performance Prediction of On-chip Global Signaling 査読

M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera

3rd Electrical Design of Avdanced Packaging and Systems Workshop, pp.87-100, Nov 2004. 2004年

配線RL抽出におけるリターンパス選択手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

DAシンポジウム 2004, pp.175-180, Jul 2004. 2004年

オンチップ伝送線路のリターン電流分布が信号波形に与える影響 — 平衡・不平衡伝送の比較 — 査読

土谷亮, 橋本昌宜, 小野寺秀俊

第17回回路とシステム軽井沢ワークショップ, pp.567-572, Apr 2004. 2004年

Representative frequency for interconnect R(f)L(f)C extraction 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 691 - 696 2004年

Representative Frequency for Interconnect R(f)L(f)C Extraction 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E86-A ( 12 ) 2942 - 2951 2003年12月

Representative frequency for interconnect R(f)L(f)C extraction 査読

A Tsuchiya, M Hashimoto, H Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E86A ( 12 ) 2942 - 2951 2003年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper discusses the frequency to extract RLC values from interconnects. In circuit design, frequency-independent equivalent circuit is widely used, and many design and analysis techniques based on this equivalent circuit are proposed so far. However in reality, characteristics of interconnects are frequency-dependent. Also pulse waveforms in digital circuits contain multiple frequency components. The frequency used for RLC extraction affects the accuracy of interconnect characterization, and hence careful determination of extraction frequency is critical. We propose a representative frequency for RLC extraction. Conventionally, representative frequencies are determined by input pulse. The proposed method decides the representative frequency based on the interconnect length, whereas conventional representative frequencies are determined by input pulse shape, period and patterns. We verify that the extraction at the proposed frequency provides the most accurate transition waveform against various input signals and interconnect structures in digital circuits.

DOI： 10.1093/ietfec/e88-a.4.885

Web of Science

周辺配線の影響を考慮したオンチップ高速信号伝送用配線構造

土谷亮

2003年3月

周辺配線の影響を考慮したオンチップ高速信号伝送用配線構造査読

土谷亮

京都大学 2003年2月

Frequency Determination for Interconnect RLC Extraction 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2003), pp.288-293, Apr 2003. 2003年

直交配線を持つオンチップ伝送線路の特性評価査読

土谷亮, 橋本昌宜, 小野寺秀俊

DA シンポジウム 2003, pp.133-138, Jul 2003. 2003年

配線R(f)L(f)C抽出のための代表周波数決定手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

第16回回路とシステム軽井沢ワークショップ, pp.61-66, Apr 2003. 2003年

VLSI 配線の伝送線路特性を考慮した駆動力決定手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

情報処理学会論文誌 43 ( 5 ) 1338 - 1347 2002年5月

Interconnect Structures for High-Speed Long-Distance Signal Transmission 査読

M. Hashimoto, D. Hiramatsu, A. Tsuchiya, H. Onodera

15th Annual IEEE International ASIC/SOC Conference, pp. 426--430, Sep 2002. 2002年

VLSI配線の伝送線路特性を考慮した駆動力決定手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

情報処理学会論文誌 2002年

長距離高速信号伝送を可能にするVLSI配線構造の検討査読

平松大輔, 土谷亮, 橋本昌宜, 小野寺秀俊

DA シンポジウム 2002, pp.155-160, Jul 2002. 2002年

Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

10th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2001), pp.377-381, Oct 2001. 2001年

VLSI配線の伝送線路化を考慮した駆動力決定手法査読

土谷亮, 小野寺秀俊

DA シンポジウム 2001, pp.241-246, Jul 2001. 2001年

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