研究者詳細 - 土谷　亮

論文 - 土谷　亮

分割表示174 件中 1 - 20 件目／全件表示 >>

Cryogenic and RF Modeling of On-Chip Passive Devices for Quantum Computer 招待査読

Akira Tsuchiya

IEEE 17th International Conference on Solid-State and Integrated Circuit Technology 1 - 3 2024年10月

Activities for Open-Source Integrated Circuits Design in Japan 招待査読

Akira Tsuchiya

9th IEEE International Conference on IC Design and Verification 130 - 133 2024年6月

Mean-Free-Path-Based Evaluation of Size Effectand Anomalous Skin Effect in On-Chip Interconnects under Cryogenic Environment 査読

Akira Tsuchiya

28th IEEE Workshop on Signal and Power Integrity 1 - 4 2024年5月

A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks 査読国際誌

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura

Microelectronics Journal 2024年3月

A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip 査読

T. Inoue, A. Tsuchiya, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura

IEEE Transactions on Circuits and Systems II 2024年

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS 招待査読

2023年10月

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS 査読

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

The 20th International SoC Conference (ISOCC) 2023年10月

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process 査読

Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

IEICE Electronics Express 20 ( 18 ) 2023年9月

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks 査読

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

IEICE Electronics Express 20 ( 14 ) 2023年7月

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS 査読

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura

IEEE International Conference on Electronics, Circuits and Systems (ICECS) 1 - 4 2023年

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS 査読

D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya and K. Kishine

International SoC Design Conference (ISOCC) 13 - 14 2023年

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS 査読国際誌

Inoue T., Tsuchiya A., Kishine K., Ito D., Takahashi Y., Nakamura M.

ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 1 - 4 2022年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 参加形態：共同（副担当）

A burst-mode transimpedance amplifier (TIA) receives burst signals, which are intermittent signals. To reduce the power consumption during the idle times, we propose a burst-mode TIA with automatic power saving in 65-nm CMOS. It enables to provide a stable operation without a DC wander effect while receiving the burst signal. The post-layout simulation results show that the designed TIA can automatically reduce the power consumption during the idle times by 54.2% compared to that during the active times.

DOI： 10.1109/ICECS202256217.2022.9970848

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85145347419&origin=inward

A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band 査読国際誌

Inoue M., Nakashioya S., Inoue T., Tsuchiya A., Kishine K.

ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 1 - 4 2022年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings

Recently, radio-wave sensors have been utilized in automotive radar and biological sensing applications. Although beamforming using an array antenna is effective method for changing the radiation directivity, the phase-shift error causes degradation of the directivity significantly. In this paper, we propose a fine-tuning phase shifter with a vector synthesizer, which enables to control the phase-shift amount continuously in 24-GHz band. From the measurement results of the fabricated phase shifter using 65-nm CMOS technology, the variable phase-shift amount over a range of 360◦ is obtained continuously. In addition, the estimated radiation patterns show that the phase-shift and amplitude errors of the fabricated phase shifter are acceptable.

DOI： 10.1109/ICECS202256217.2022.9970921

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85145359534&origin=inward

A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA 査読国際誌

Okamoto M., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 55 - 56 2022年10月

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：Proceedings - International SoC Design Conference 2022, ISOCC 2022 参加形態：共同（副担当）

We propose a method for implementing an LSTM-based multiple-people identification system on a small-scale FPGA. To reduce the hardware-resource usage, we introduce a digit adjustment and bit reduction method for converting the floating-point type to the fixed-point type with high precision. It enables not only to reduce the hardware-resource usage without degrading the identification accuracy but also to shorten the computation time by 50% compared to that of the conventional floating-point type.

DOI： 10.1109/ISOCC56007.2022.10031374

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85148419807&origin=inward

Smart Computational Resource Distribution System with Automatic Classification Interface for CPS 査読国際誌

Teramura Y., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 101 - 102 2022年10月

This paper describes a proposal for a classification interface for computational resources distribution in CPS. The classification interface enables to distribute processing to the different computational resources (CPU and FPGA) automatically depending on the type of the processing. As a result, the total processing time is shortened by 50.9% compared to that of the system without the classification interface.

DOI： 10.1109/ISOCC56007.2022.10031427

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85148441659&origin=inward

Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing 査読国際誌

Shimohane S., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 338 - 339 2022年10月

In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAMbased system.

DOI： 10.1109/ISOCC56007.2022.10031293

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85148465121&origin=inward

A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS 査読国際誌

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura

65th IEEE International Midwest Symposium on Circuits and Systems 1 - 4 2022年8月

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad 査読国際誌

A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura

IEEE 65th International Midwest Symposium on Circuits and Systems 1 - 4 2022年8月

Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit 査読

Takahashi Y., Ito D., Namamura M., Tsuchiya A., Inoue T., Kishine K.

Electronics (Switzerland) 11 ( 6 ) 2022年3月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Electronics (Switzerland)

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dBΩ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 µm × 225 µm.

DOI： 10.3390/electronics11060854

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85126023979&origin=inward

Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion 査読国際誌

Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 579 - 582 2022年2月

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