Faculty Profiles - INOUE Toshiyuki

Papers - INOUE Toshiyuki

Division display1 - 20 of about 80／ All the affair displays >>

A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip Reviewed International journal

T. Inoue, A. Tsuchiya, K. Kishine, Y. Takahashi, D. Ito, and M. Nakamura

IEEE Transactions on Circuits and Systems II: Express Briefs 71 ( 5 ) 2514 - 2518 2024.3

A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks Reviewed International journal

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, and Makoto Nakamura

Microelectronics Journal 145 106120 2024.3

Delay Circuit Design for Differential Detection in Intra- Vehicle Optical Networks Invited Reviewed International journal

T. Inoue, A. Tsuchiya, K. Kishine, D Ito, Y. Takahashi, and M. Nakamura

2025 IEEE the 14th International Conference on Communications, Circuits, and Systems (ICCCAS 2025) 2025.5

A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip Reviewed International journal

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

2024 IEEE 37th International System-on-Chip Conference (SOCC) 2024.9

A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS Reviewed

Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, and Keiji Kishine

2024 International Conference on Electronics, Information, and Communication (ICEIC) 2024.3

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS Reviewed

D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya, and K. Kishine

2023 20th International SoC Design Conference (ISOCC) 13 - 14 2024.1

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS Invited Reviewed

A. Tsuchiya, T. Inoue, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

2023 IEEE 15th International Conference on ASIC (ASICON) 1 - 2 2024.1

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS Reviewed

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 1 - 4 2024.1

Low-power and Small-area 4-ch 25-Gb/s Transimpedance Amplifiers in 65-nm CMOS Process Reviewed

Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

IEICE Electronics Express 20 ( 18 ) 1 - 6 2023.9

10 Gb/s burst-mode driver circuit with on-chip bias switch for in-vehicle optical networks Reviewed International journal

Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

IEICE Electronics Express 20 ( 12 ) 2023.7

Burst-mode driver circuit with on-chip bias tee for in-Vehicle optical networks Reviewed International journal

Daisuke Ito, Yasuhuiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

2022 International Conference on Analog VLSI Circuits (AVIC) 2022.11

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS Reviewed

Inoue T., Tsuchiya A., Kishine K., Ito D., Takahashi Y., Nakamura M.

ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 2022.10

Language：English Publishing type：Research paper (international conference proceedings) Publisher：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings Participation form：Joint(The main charge)

A burst-mode transimpedance amplifier (TIA) receives burst signals, which are intermittent signals. To reduce the power consumption during the idle times, we propose a burst-mode TIA with automatic power saving in 65-nm CMOS. It enables to provide a stable operation without a DC wander effect while receiving the burst signal. The post-layout simulation results show that the designed TIA can automatically reduce the power consumption during the idle times by 54.2% compared to that during the active times.

DOI： 10.1109/ICECS202256217.2022.9970848

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85145347419&origin=inward

A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band Reviewed International journal

Inoue M., Nakashioya S., Inoue T., Tsuchiya A., Kishine K.

ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 2022.10

Language：English Publishing type：Research paper (scientific journal) Publisher：ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings Participation form：Joint(The vice charge)

Recently, radio-wave sensors have been utilized in automotive radar and biological sensing applications. Although beamforming using an array antenna is effective method for changing the radiation directivity, the phase-shift error causes degradation of the directivity significantly. In this paper, we propose a fine-tuning phase shifter with a vector synthesizer, which enables to control the phase-shift amount continuously in 24-GHz band. From the measurement results of the fabricated phase shifter using 65-nm CMOS technology, the variable phase-shift amount over a range of 360◦ is obtained continuously. In addition, the estimated radiation patterns show that the phase-shift and amplitude errors of the fabricated phase shifter are acceptable.

DOI： 10.1109/ICECS202256217.2022.9970921

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85145359534&origin=inward

A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA Reviewed International journal

Okamoto M., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 55 - 56 2022.10

Language：English Publishing type：Research paper (scientific journal) Publisher：Proceedings - International SoC Design Conference 2022, ISOCC 2022 Participation form：Joint(The vice charge)

We propose a method for implementing an LSTM-based multiple-people identification system on a small-scale FPGA. To reduce the hardware-resource usage, we introduce a digit adjustment and bit reduction method for converting the floating-point type to the fixed-point type with high precision. It enables not only to reduce the hardware-resource usage without degrading the identification accuracy but also to shorten the computation time by 50% compared to that of the conventional floating-point type.

DOI： 10.1109/ISOCC56007.2022.10031374

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85148419807&origin=inward

Smart Computational Resource Distribution System with Automatic Classification Interface for CPS Reviewed International journal

Teramura Y., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 101 - 102 2022.10

Language：English Publishing type：Research paper (scientific journal) Publisher：Proceedings - International SoC Design Conference 2022, ISOCC 2022 Participation form：Joint(The vice charge)

This paper describes a proposal for a classification interface for computational resources distribution in CPS. The classification interface enables to distribute processing to the different computational resources (CPU and FPGA) automatically depending on the type of the processing. As a result, the total processing time is shortened by 50.9% compared to that of the system without the classification interface.

DOI： 10.1109/ISOCC56007.2022.10031427

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85148441659&origin=inward

Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing Reviewed International journal

Shimohane S., Inoue T., Tsuchiya A., Kishine K.

Proceedings - International SoC Design Conference 2022, ISOCC 2022 338 - 339 2022.10

Language：English Publishing type：Research paper (scientific journal) Publisher：Proceedings - International SoC Design Conference 2022, ISOCC 2022 Participation form：Joint(The vice charge)

In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAMbased system.

DOI： 10.1109/ISOCC56007.2022.10031293

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85148465121&origin=inward

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad Reviewed International journal

A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito and M. Nakamura

2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) 2022.8

A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS, Fukuoka, Japan, 2022, pp. 1-4, Reviewed International journal

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi and M. Nakamura,

2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) 2022.8

Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit Reviewed

Y. Takahashi, D. Ito, M. Nakamura, A. Tsuchiya, T. Inoue, and K. Kishine

Electronics 11 ( 6 ) 2022.3

Language：English Publishing type：Research paper (scientific journal) Publisher：MDPI Participation form：Joint(The vice charge)

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dBΩ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 µm × 225 µm.

DOI： 10.3390/electronics11060854

Scopus

Other Link： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85126023979&origin=inward

Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion Reviewed International journal

R. Yamazaki, Y. Teramura, T. Inoue, A. Tsuchiya, and K. Kishine

International Conference on Electronics, Information, and Communication (ICEIC) 2022 2022.2

　PREV- NEXT 　

<INOUE Toshiyuki>

Papers - INOUE Toshiyuki