Organization
Faculty of Advanced Engineering
Department
School of Engineering Department of Electronic Systems Engineering
Title
Professor
External link
KISHINE Keiji
Degree
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Doctor(Informatics) ( 2006.3 Kyoto University )
Research Field
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LSI design
Research Experience
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The University of Shiga Prefecture School of Engineering Department of Electronic Systems Engineering Professor
2016.4
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The University of Shiga Prefecture School of Engineering Department of Electronic Systems Engineering Associate Professor
2008.4 - 2016.3
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NIPPON TELEGRAM NAD TELEPHONE
2007.4 - 2008.3
Country：Japan
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NIPPON TELEGRAPH AND TELEPHONE Chief Researcher
2004.10 - 2007.3
Country：Japan
Association Memberships
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日本物理学会
2008.4
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電気学会
2008.4
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電子情報通信学会
2008.4
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IEEE
2008.4
Available Technology
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応用システムとハードウェアの最適融合
Papers
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A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip
T. Inoue, A. Tsuchiya, K. Kishine, Y. Takahashi, D. Ito, and M. Nakamura
IEEE Transactions on Circuits and Systems II: Express Briefs 71 ( 5 ) 2024.3
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A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks Reviewed
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, and Makoto Nakamura
Microelectronics Journal 145 106120 2024.3
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4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS Reviewed
D. Ito, Y. Takahashi, M. Nakamura, T. Inoue, A. Tsuchiya, and K. Kishine
2023 20th International SoC Design Conference (ISOCC) 13 - 14 2024.3
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igh-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS Reviewed
A. Tsuchiya, T. Inoue, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura
2023 IEEE 15th International Conference on ASIC (ASICON) 1 - 2 2024.1
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A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS Reviewed
T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura
2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 1 - 4 2024.1
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10 Gb／s burst-mode driver circuit with on-chip bias switch for in-vehicle optical networks Reviewed
Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
EICE Electronics Express 20 12 2023.7
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Burst-mode driver circuit with on-chip bias tee for in-Vehicle optical networks Reviewed International journal
Daisuke Ito, Yasuhuiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
2022 International Conference on Analog VLSI Circuits (AVIC) 55 - 69 2022.11
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A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band Reviewed International journal
Inoue M., Nakashioya S., Inoue T., Tsuchiya A., Kishine K.
ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings ICECS 2022 - 29th IEEE International Conference on Electronics, Circuits and Systems, Proceedings 2022.10
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Implementation of High-Speed LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA Reviewed International journal
Ukyo Yoshimura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022.2
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Capacitor Under Pad for Small Area Integration of High-SpeedSignal-to-Diff erential Amplifi er Reviewed International journal
A. Tsuchiya, T. Inoue, K. Kishine, Y. Takahashi, D. Ito, and M. Nakamura
International Conference on Electronics, Information, andCommunication (ICEIC) 2022.2
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A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks Reviewed International journal
T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura
2021.11
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Dynamic Memory Access Control for Accelerating FPGA-based Image Processing Reviewed International journal
K. Nishiguchi, T. Inoue, R. Yamazaki, K. Ogohara, A. Tsuchiya, and K. Kishine
１０ ( 5 ) ４１６ - ４２３ 2021.10
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5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS Reviewed International journal
Yudai Ichii, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2021.2
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Processing Time Reduction for JPEG CompressionUsing Pixel Array Conversion Reviewed International journal
Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
2020.10
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Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS Reviewed International journal
Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
Journal of Semiconductor Technology and Science 20 ( 2 ) 2020.4
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Optimization Technique of Memory Traffic for FPGA-Based Image Processing System Reviewed International journal
Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara, Keiji Kishine
2019.10
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Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS Reviewed International journal
Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2019.10
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Frequency Discriminator Using a Simple AD Converter for Interface Systems Reviewed International journal
Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2019.10
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Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier Reviewed International journal
Shinya Tanimura, Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, and Keiji Kishine
32nd IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC 2019) 2019.9
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FPGA-based binary labeling signal transmission system Reviewed International journal
Inoue T., Nomura K., Noguchi R., Koda N., Tsuchiya A., Kishine K.
Journal of Semiconductor Technology and Science 19 ( 3 ) 2019.6
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A 25-Gb/s Low-Power Clock and Data Recovery with an ActiveStabilizing CML-CMOS Conversion Reviewed International journal
Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
The 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018) 2018.12
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Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology Reviewed International journal
Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, and Hidetoshi Onodera
The 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2018) 2018.8
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A 25-Gb/s 13 mW Clock and Data Recovery Using C²MOS D-Flip-Flop in 65-nm CMOS Reviewed International journal
yosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakamoto, and Makoto Nakamura
VLSI Design, Automation and Test (VLSI-DAT2018) 1 - 4 2018.4
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10-Gb/s Data Frame Generation Circuit with Frequency Modulation in 65-nm CMOS Reviewed International journal
Hiromu Uemura, Kosuke Furuichi, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine
IEIE JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE(IEIE JSTS) 18 ( 2 ) 238 - 245 2018.4
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Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS Reviewed International journal
Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine
IEIE JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE(IEIE JSTS) 17 ( 6 ) 742 - 749 2017.12
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Simple and Low Power Highly Sensitive Frequency Demodulator Circuit for 10-Gb/s Transmission System for Labeling Signal Reviewed International journal
Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, and Keiji Kishine
IEIE JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE(IEIE JSTS) 17 ( 6 ) 733 - 740 2017.12
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FPGA-Based Transceiver Circuit for Labeling Signal Transmission System Reviewed International journal
Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
2017.11
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Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS Reviewed International journal
Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, and Makoto Nakamura
2017.11
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Compact Implementation IIR filter in FPGA for Noise Reduction of Sensor Signal Reviewed International journal
Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
2017.11
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25-Gb/s Clock and Data Recovery IC Using Latch Load Combined with CML Buffer Circuit for Delay Generation with 65-nm CMOS Reviewed International journal
Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka and Keiji Kishine
IEEE International Symposium on Circuits and Systems (ISCAS2017) 2017.5
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Cross Current Suppression Control for Parallel Operation System Contructed with Two Electric Power Converters under Different Output Reviewed International journal
Ryota Fujisawa, Hiromi Inaba, Keiji Kishine, Keisuke Ishikura, and Kazuki Ikebata
The 19th International Conference on Electrical Machines and Systems (ICEMS2016) 2016.11
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36-Gb/s CDR IC using simple passive loop filter combined with a passive load in phase detector Reviewed International journal
Keiji Kishine, Hiroshi Inoue, Hiromu Uemura, Kosuke Furuichi, Natsuyuki Koda , Makoto Nakamura ,Akira Tsuchiya,Hiromi Inaba
2016.10
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Design of High-Linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS Reviewed International journal
Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine
International SoC Design Conference (ISOCC2016) 2016.10
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Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system Reviewed International journal
Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, and Keiji Kishine
International SoC Design Conference (ISOCC2016) 2016.10
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Simple Routing Control System for 10 Gb/s Data Transmission Using a Frequency Modulation Technique Reviewed International journal
Daichi Omoto, Keiji Kishine, Hiromi Inaba, and Tomoki Tanaka
IEIE transactions on smart processing and computing 5 ( 3 ) 207 - 213 2016.6
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Low-jitter design method based on ωn-domain jitter analysis for 10 Gbit/s clock Reviewed
K. Kishine, H. Inaba, Makoto Nakamura, Mitsuo Nakamura, Y. Ohtomo and H. Onodera
IET Electron. Letters 45 ( 16 ) 800 - 804 2009.7
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A Jitter Suppression Technique for a 2.48832Gb/s Clock and Data Recovery Circuit Reviewed
Kiyoshi Ishii, Keiji Kishine and Haruhiko Ichino
Trans. Circuits Syst. II 49 ( 4 ) 266 - 272 2002.4
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Loop-Parameter Optimization of a PLL for a Low-Jitter 2.5 Gb/s One-chip Optical Receiver IC with 1:8 DEMUX Reviewed
Keiji Kishine and Haruhiko Ichino
IEEE J. Solid-State Circuits 37 ( 1 ) 38 - 50 2002.1
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Techniques for Widening Lock and Pull-in Ranges and Suppressing Jitter in Clock and Data Recovery ICs -Duplicated Loop Control CDR- Reviewed
Keiji Kishine, Noboru Ishihara and Haruhiko Ichino,
IEICE Trans. Electron., E-84-C ( 4 ) 460 - 469 2001.4
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A jitter suppression technique for a clock multiplier," IEICE Trans. Electron., Reviewed
Kiyoshi Ishii, Keiji Kishine and Haruhiko Ichino,
IEICE Trans. Electron., E-83-C ( 4 ) 647 - 651 2000.4
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A 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LANs and WANs"jointly worked" Reviewed
Keiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi and Haruhiko Ichino
IEEE J. Solid State Circuits 34 ( 6 ) 805 - 812 1999.6
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2.5-Gb/s clock and data recovery circuit IC using novel duplicated PLL Technique Reviewed
IEE Electron. Letters 35 ( 5 ) 360 - 361 1999.3
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Low-Power 2.5Gb/s Si-Bipolar IC Chipset for Optical Receivers and Transmitters Using Low-Voltage and Adjustment-Free Circuit Techniques Reviewed
Masaki Hirose, Keiji Kishine, Haruhiko Ichino and Noboru Ishihara
IEICE Trans. Electron. E-83-C ( 4 ) 647 - 651 1999.3
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Jitter-suppressed low-power 2.5\,Gb/s clock and data recovery IC without high-Q components"jointly worked" Reviewed
Keiji Kishine, Noboru Ishihara and Haruhiko Ichino
IEE Electron. Letters 33 ( 18 ) 1545 - 1547 1997.8
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A High-Speed, Low-Power Bipolar Digital Circuit for Gb/s LSI's: Current Mirror Control Logic "jointly worked" Reviewed
Keiji Kishine, Yoshiji Kobayashi and Haruhiko Ichino
IEEE J. Solid State Circuits 32 ( 2 ) 215 - 221 1997.2
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Energy Losses of 12-32 keV H+, He+ and N+ Ions at Glancing Angle Scattering from Clean Surfaces of Silicon Crystals Reviewed
Kazumasa Narumi, Yoshikazu Fujii, Keiji Kishine, Shinsuke Fujiwara, Kenji Kimura and Michi-hiko Mannami
Journal of the Physical Society of Japan 62 ( 5 ) 1603 - 1611 1993.5
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Contribution of inner shell electrons to position-dependent stopping powers of a crystal surface Reviewed
Kazumasa Narumi, Yoshikazu Fujii, Keiji Kishine, Hiroshi Kurakake, Kenji Kimura and Michi-hiko Mannami
Surface science 293 ( 3 ) 152 - 159 1993.5
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Energy loss of 0.7-MeV He ions due to the dynamic response of surface electrons Reviewed
Yoshikazu Fujii, Keiji Kishine, Kazumasa Narumi, Kenji Kimura and Michi-hiko Mannami
Phys. Rev. A 47 2047 - 2054 1993.3
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Dynamic response of surface electrons to energetic ions at glancing angle scattering from crystal surfaces Reviewed
Yoshikazu Fujii, Kazumasa Narumi , Keiji Kishine, Kenji Kimura and Michi-hiko Mannami
Nuclear Instruments and Methods in Physics Research Sec. B 67 ( 41278 ) 82 - 86 1992.4
Books etc
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体センシング技術開発の現状と研究開発のポイント
井上敏之, 岸根桂路（ Role： Contributor , Original_author： 井上敏之, 岸根桂路）
2024.2 （ ISBN:978-4-86502-263-6 ）
Research Projects
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A ultra-high speed integrated circuit design
2008.4
Advanced Technology Development Research integrated circuit low power ultra-high speed communication system
Presentations
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静電容量を利用した液滴の接触角推定における対応範囲拡大の検討
小谷口朋大, 土谷亮, 井上敏之,岸根桂路
集積回路研究会(ICD) 2020.11 電子情報通信学会
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マイクロ波センサ回転制御による広範囲検出手法の確立
柏木雅哉, 吉村侑恭, 井上敏之,岸根桂路,土谷亮
電子情報通信学会ソサエティ大会 2020.9 電子情報通信学会
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シングルチャネルマルチポート制御システムにおける送受信回路デジタル化の検討
今城篤人・井上敏之・木村山紫郎・西口健太・土谷 亮・岸根桂路
電子情報通信学会総合大会 2020.3 電子情報通信学会
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非接触心拍計測システムおけるディジタルフィルタ回路規模削減手法の検討
吉村侑恭・井上敏之・土谷 亮・岸根桂路
電子情報通信学会総合大会 2020.3 電子情報通信学会
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ブロック方式におけるモデル化誤差を考慮した配線ブロック数と面積の関係
岩田智成・土谷 亮・谷村信哉・井上俊之・岸根桂路
電子情報通信学会総合大会 2020.3 電子情報通信学会
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RGC-TIAにおける多層インダクタによる面積効率向上効果の評価
田中大夢,土谷亮,谷村信哉,井上敏之,岸根桂路
電子情報通信学会総合大会 2020.3 電子情報通信学会
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RGC-TIAの利得が帯域と入力換算雑音の関係に与える影響
中田吉弥, 土谷亮, 谷村信哉, 井上敏之, 岸根桂路
電子情報通信学会ソサイエティ大会 2019.9 電子情報通信学会
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マイクロ波センサ直交信号を用いたFPGAによるデータ取得時間短縮手法の検討
吉村侑恭，西口健太，井上敏之，土谷亮，岸根桂路
電子情報通信学会総合大会 2019.3 電子情報通信学会
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シングルチャネルシステム実現に向けた周波数識別回路の検討
今城篤人，野口凌輔，井上敏之，土谷亮，岸根桂路
電子情報通信学会総合大会 2019.3 電子情報通信学会
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多チャンネル実装トランスインピーダンスアンプにおける電源ノイズ削減フィルタの設計手法
谷村信哉，土谷亮，野口凌輔，井上敏之，岸根桂路
電子情報通信学会総合大会 2019.3 電子情報通信学会
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キャリア周波数識別の高分解能化を目指したディスチャージ遅延回路の検討
木村山紫郎，井上敏之，野口凌輔，土谷亮，岸根桂路
電気関係学会関西連合大会 2018.12 電気関係学会関西連合大会
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脈拍センサを用いた呼吸統制下における自律神経状態推定システムの検討
牧将平，井上敏之，土谷亮，岸根桂路
電気関係学会関西連合大会 2018.12 電気関係学会関西連合大会
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入出力インタフェースを実装したFPGAリアルタイム画像処理システムの構築
西口健太，井上敏之，小郷原一智，土谷亮，岸根桂路
電子情報通信学会ソサイエティ大会 2018.9 電子情報通信学会
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群遅延偏差の線形近似による多段構成TIAのジッタ低減
谷村信哉，土谷亮，井上敏之，岸根桂路
LSIとシステムのワークショップ 2018.5 LSIとシステムのワークショップ
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ウェアラブルセンサと簡易無線モジュールによる筋疲労計測システムの検討
水野佑哉，牧将平，荒内航貴，井上敏之，土谷亮，岸根桂路
電子情報通信学会総合大会 2018.3 電子情報通信学会
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100-Gb/s低電力光通信トランシーバ用CML-CMOSレベル変換回路の検討
野口凌輔，香田夏幸，野村幸平，土谷亮，井上敏之，岸根桂路
電子情報通信学会総合大会 2018.3 電子情報通信学会
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XBeeと脈波センサを用いた自律神経機能検知システムの検討
牧将平，荒内航貴，水野佑哉，井上敏之，土谷亮，岸根桂路
電気学会電子回路研究会 2018.3 電気学会
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野外における2.4Ghz帯無線モジュールの通信可能距離の実測評価
高杉陽介，土谷亮，井上敏之，岸根桂路
ICD/MW共催研究会 2018.3 ICD/MW共催研究会
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XBeeと複数ウェアラブルセンサによる高齢者見守り検知システムの検討
牧将平，荒内航貴，森本安紀，土谷亮，井上敏之，岸根桂路
電気関係学会連合大会 2017.11 電気関係学会連合大会
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FPGAを用いたFIRフィルタによる脈拍センサ信号の雑音除去
荒内航貴，森本安紀，作田健，植村宙夢，香田夏幸，岸根桂路
電子情報通信学会総合大会 2017.3 電子情報通信学会
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FPGAによるフレーム信号変調システムの検討
野村幸平，植村宙夢，古市康祐，岸根桂路
電子情報通信学会総合大会 2017.3 電子情報通信学会
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ラべリング信号伝送システムにおける受信回路高速化の検討
香田夏幸，古市康祐，植村宙夢，荒内航貴，野村幸平，岸根桂路
電子情報通信学会総合大会 2017.3 電子情報通信学会
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FPGAを用いた変調回路に関する検討
野村幸平，植村宙夢，古市康祐，岸根桂路
電気関係学会関西連合大会 2016.11 電子情報通信学会
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エンファシス回路によるハーフレート識別回路の広帯域化に関する検討
寺本慎也，古市康祐，植村宙夢，岸根桂路
電気関係学会関西連合大会 2016.11 電子情報通信学会
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FPGAを用いたFIRフィルタによる生体センサ信号の雑音除去の検討
荒内航貴，森本安紀，作田建，岸根桂路
電気関係学会関西連合大会 2016.11 電子情報通信学会
Teaching Experience
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集積回路設計基礎
2012.4 - 2013.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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情報通信工学
2012.4 - 2013.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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基礎電気電子回路
2012.4 - 2013.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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電子システム工学セミナー
2012.4 - 2013.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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電子システム工学実験Ⅳ
2012.4 - 2013.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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電子システム工学実験Ⅰ
2012.4 - 2013.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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集積システム設計論
2012.4 - 2013.3 Institution：滋賀県立大学
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基礎電気電子回路
2009.4 - 2010.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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基礎電気電子回路
2008.4 - 2009.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)
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電子システム工学セミナー
2008.4 - 2009.3 Institution：滋賀県立大学
Level：Undergraduate (specialized)