Faculty Profiles - TSUCHIYA Akira

Papers - TSUCHIYA Akira

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Low-Power Regulated Cascode CMOS Transimpedance Amplifier with Local Feedback Circuit Reviewed

Takahashi Y., Ito D., Namamura M., Tsuchiya A., Inoue T., Kishine K.

Electronics (Switzerland) 11 ( 6 ) 2022.3

Language：English Publishing type：Research paper (scientific journal) Publisher：Electronics (Switzerland)

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with the conventional global-feedback technique, the proposed TIA has the advantages of a wider bandwidth, and lower power dissipation. The schematic and characteristics of the proposed TIA circuit are described. Moreover, the proposed TIA employs inductive peaking to increase bandwidth. The TIA is implemented using a 65 nm complementary metal oxide semiconductor (CMOS) technology and consumes 23.9 mW with a supply voltage of 1.0 V. Using a back-annotated simulation, we obtained the following characteristics: a gain of 46 dBΩ and −3 dB frequency of 11.4 GHz. TIA occupies an area of 366 µm × 225 µm.

DOI： 10.3390/electronics11060854

Scopus

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Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion Reviewed International journal

Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 579 - 582 2022.2

A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver Reviewed International journal

Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 644 - 647 2022.2

Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems Reviewed International journal

Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 616 - 619 2022.2

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier Reviewed International journal

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, and Makoto Nakamura

International Conference on Electronics, Information, and Communication 640 - 643 2022.2

Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS Reviewed International journal

Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

The 27th Asia and South Pacific Design Automation Conference 96 - 97 2022.1

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks Reviewed International journal

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) 1 - 6 2021.11

Dynamic Memory Access Control for Accelerating FPGA-based Image Processing Reviewed International journal

Kenta Nishiguchi, Toshiyuki Inoue, Rei Yamazaki, Kazunori Ogohara, Akira Tsuchiya, Keiji Kishine

Journal of Semiconductor Technology and Science 21 ( 1 ) 29 - 38 2021.2

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS Reviewed

Ichii Y., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021.1

Language：English Publishing type：Research paper (scientific journal) Publisher：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

This paper proposes a 5-Gb/s four-level pulse amplitude modulation (PAM4) transmitter using compensation circuit in data transmission systems. In PAM4 systems, the signal amplitude requires smaller rising and falling times. To achieve this, we adopted an analog feed forward equalizing (FFE) for the compensation in PAM4 transmitter. To confirm the advantage of the proposed technique, we fabricated a 5-Gb/s PAM4 transmitter IC in an 180-nm CMOS process for this work. The measured rising and falling times were 18% and 13% smaller than those without FFE, respectively.

DOI： 10.1109/ICEIC51217.2021.9369819

Scopus

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Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA Reviewed

Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021.1

Language：English Publishing type：Research paper (scientific journal) Publisher：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Regression and classification are necessary for biometric systems and carried out using machine learning. A method for regression and classification is long short-term memory (LSTM). We proposed and implemented algorithms for low-energy LSTM for the regression of microwave-sensor signals into a small-scale FPGA. We found that our FPGA-based parallel (including unrolled)-pipelined algorithm decreased the computation time by 95% compared with the FPGA-based sequential algorithm. In addition, the amount of energy consumption with the proposed algorithm was reduced by 92% and 91% compared with that with a high-end GPU and CPU, respectively.

DOI： 10.1109/ICEIC51217.2021.9369806

Scopus

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Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers Reviewed International journal

Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

Asia-South Pacific Design Automation Conference 15 - 16 2021.1

A Method for Accelerating the Inference Process of FPGA-based LSTM for Biometric Systems Reviewed

Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

IEIE Transactions on Smart Processing and Computing 10 ( 5 ) 416 - 423 2021.1

Language：English Publishing type：Research paper (scientific journal) Publisher：IEIE Transactions on Smart Processing and Computing

Biometric systems require the regression and classification of biological sensing data, which are both carried out using machine learning. Long short-term memory (LSTM) is one of the most common methods used for regression and classification. We have developed and implemented a low-energy LSTM algorithm for the regression of microwave sensor signals in a small-scale FPGA. Experimental results show that the FPGA-based parallel-pipelined unrolled algorithm can reduce the computation time by 95% compared to an FPGA-based sequential algorithm. In addition, we found that the power consumption can be reduced by 92% and 91% compared to that obtained with a high-end GPU and CPU, respectively.

DOI： 10.5573/IEIESPC.2021.10.5.416

Scopus

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Processing Time Reduction for JPEG Compression Using Pixel Array Conversion Reviewed International journal

Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

17th International SoC Design Conference 2020.10

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS Reviewed International journal

Akira TSUCHIYA, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, Hidetoshi ONODERA

IEiCE Transactions on Electronics E103-C ( 10 ) 489 - 496 2020.10

Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking Invited Reviewed International journal

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

2020 IEEE International Symposium on Radio-Frequency Integration Technology 12 - 14 2020.9

Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS Reviewed

Inoue T., Tsuchiya A., Kishine K.

Journal of Semiconductor Technology and Science 20 ( 2 ) 177 - 186 2020.4

Language：English Publishing type：Research paper (scientific journal) Publisher：Journal of Semiconductor Technology and Science Participation form：Joint(The vice charge)

© 2020, Institute of Electronics Engineers of Korea. All rights reserved. We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, band-width, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-mm CMOS type.

DOI： 10.5573/JSTS.2020.20.2.177

Scopus

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Capacitive Sensor for Contact Angle Estimation of Droplet on Microfluidic Chip Reviewed International journal

Akira Tsuchiya, Toshiyuki Inoue and Keiji Kishine

2019 Asia-Pacific Microwave Conference 2019.12

Frequency Discriminator Using a Simple AD Converter for Interface Systems Reviewed International journal

Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

16th International SoC Design Conference 2019.10

Optimization Technique of Memory Traffic for FPGA-Based Image Processing System Reviewed International journal

Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara and Keiji Kishine

16th International SoC Design Conference 2019.10

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS Reviewed International journal

Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

16th International SoC Design Conference 2019.10

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Papers - TSUCHIYA Akira