Faculty Profiles - TSUCHIYA Akira

Papers - TSUCHIYA Akira

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Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling Reviewed

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Electronics E90-C ( 6 ) 1267 - 1273 2007.6

Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

T. Kuboki, A. Tsuchiya, H. Onodera

IEICE Transactions on Electronics E90-C ( 6 ) 1274 - 1281 2007.6

Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS E90C ( 6 ) 1274 - 1281 2007.6

Language：English Publishing type：Research paper (scientific journal) Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip trans mission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.

DOI： 10.1093/ietele/e90-c.6.1274

Web of Science

Analytical estimation of interconnect loss due to dummy fills Reviewed

20 19 - 22 2007.4

A 10Gbps/channel on-chip signaling circuit with an impedance-unmatched CML driver in 90nm CMOS technology Reviewed

T. Kuboki, A. Tsuchiya, H. Onodera

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 120 - 121 2007

Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration Reviewed

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 869 - 872 2007

Language：English Publishing type：Research paper (international conference proceedings) Publisher：Institute of Electrical and Electronics Engineers Inc.

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified. We also apply the proposed model to design trade-off analysis.

DOI： 10.1109/CICC.2007.4405866

Scopus

Measurement of interconnect loss due to dummy fills Reviewed

Akira Tsuchiya, Hidetoshi Onodera

2007 IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS 241 - 244 2007

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

This paper reports measurement results of on-chip interconnects with CMP dummy fill. CMP dummy fill is a floating metal for metal density adjustment. In high frequency above 10GHz, the eddy current induced in dummy fills affects the interconnect loss. We fabricated test structures of on-chip interconnect with dummy fills. From the measurement results, the effect of the dummy fills on the wire resistance is not negligible even if the ground wires are adjacent to the signal wire. The dummy fills in the upper/lower metal layer affect the wire resistance and the resistance increases by 20% at 50GHz.

DOI： 10.1109/SPI.2007.4512261

Web of Science

Effect of dummy fills on high-frequency characteristics of on-chip interconnects Reviewed

Akira Tsuchiya, Hidetoshi Onodera

Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006 275 - 278 2007

Language：English Publishing type：Research paper (international conference proceedings)

This paper discusses the effect of dummy fills on on-chip interconnect characteristics. The effect of dummy fills has been discussed from the viewpoint of the capacitance. However in high frequency, the magnetic coupling between the signal current and the eddy current in the dummy fills is not negligible. We evaluate the characteristics of on-chip interconnects with dummy fills by a 3D field solver. The size and the location of dummy fills are varied. We also evaluate the effect of dummy fills in the other interconnect layers. Experimental results shows that the impact of the dummy fills on the resistance and the attenuation is not negligible in high frequency such as 50GHz, and the dummy fills in the other layers have strong effect to the interconnect characteristics. The increase of the attenuation constant due to the dummy fills becomes 20% in maximum. ©2006 IEEE.

DOI： 10.1109/SPI.2006.289243

Scopus

Effect of Dummy Fills on High frequency characteristics of Spiral Inductor Reviewed

Akira Tsuchiya, Hidetoshi Onodera

14th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2007), pp.256-260, Oct 2007. 2007

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

Proceedings - 10th IEEE Workshop on Signal Propagation on Interconnects, SPI 2006 227 - 230 2007

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

This paper proposes a simple yet sufficient Si-substrate modeling for interconnect resistance and inductance extraction. The proposed modeling expresses Si-substrate as four filaments in a filament-based extractor. Although the number of filaments is small, extracted loop inductances and resistances show accurate frequency dependence resulting from the proximity effect. We experimentally prove the accuracy using FEM (Finite Element Method) based simulations of electromagnetic fields. We also show a method to determine optimal size of the four filaments. The proposed model realizes substrate-aware extraction in SoC design flow.

DOI： 10.1109/SPI.2006.289229

Web of Science

Worst-case delay analysis considering the variability of transistors and interconnects Reviewed

T. Fukuoka, A. Tsuchiya, H. Onodera

Proceedings of the International Symposium on Physical Design 35 - 42 2007

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 12 ) 3560 - 3568 2006.12

Interconnect RL extraction based on transfer characteristics of transmission-line Reviewed

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E89-A ( 12 ) 3585 - 3593 2006.12

Interconnect RL extraction based on transfer characteristics of transmission-line Reviewed

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3585 - 3593 2006.12

Language：English Publishing type：Research paper (scientific journal) Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. Experimental results show that the proposed method provides accurate transition waveforms over various interconnect topologies.

DOI： 10.1093/ietfec/e89-a.12.3585

Web of Science

Si-substrate modeling toward substrate-aware interconnect resistance and inductance extraction in SoC design Reviewed

Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E89A ( 12 ) 3560 - 3568 2006.12

Language：English Publishing type：Research paper (scientific journal) Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

DOI： 10.1093/ietfec/e89-a.12.3560

Web of Science

トランジスタと配線構造のばらつきを考慮した遅延時間のワーストケース解析 Reviewed

福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2006 ( 7 ) 13 - 18 2006.7

Performance prediction of on-chip high-speed signaling Reviewed

19 393 - 398 2006.4

Low-power design of CML driver for on-chip transmission-lines using impedance-unmatched driver Reviewed

19 387 - 392 2006.4

Alternate self-shielding for high-speed and reliable on-chip global interconnect Reviewed

Y. Yuyama, A. Tsuchiya, K. Kobayashi, H. Onodera

IEICE Transactions on Electronics E89-C ( 3 ) 327 - 333 2006.3

Alternate self-shielding for high-speed and reliable on-chip global interconnect Reviewed

Y Yuyama, A Tsuchiya, K Kobayashi, H Onodera

IEICE TRANSACTIONS ON ELECTRONICS E89C ( 3 ) 327 - 333 2006.3

Language：English Publishing type：Research paper (scientific journal) Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.

DOI： 10.1093/ietele/e89-c.3.327

Web of Science

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Papers - TSUCHIYA Akira