Faculty Profiles - TSUCHIYA Akira

Papers - TSUCHIYA Akira

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A wireless neural recording system with a precision motorized microdrive for freely behaving animals Reviewed

Taku Hasegawa, Hisataka Fujimoto, Koichiro Tashiro, Mayu Nonomura, Akira Tsuchiya, Dai Watanabe

SCIENTIFIC REPORTS 5 7853 2015.1

Language：English Publishing type：Research paper (scientific journal) Publisher：NATURE PUBLISHING GROUP

The brain is composed of many different types of neurons. Therefore, analysis of brain activity with single-cell resolution could provide fundamental insights into brain mechanisms. However, the electrical signal of an individual neuron is very small, and precise isolation of single neuronal activity from moving subjects is still challenging. To measure single-unit signals in actively behaving states, establishment of technologies that enable fine control of electrode positioning and strict spike sorting is essential. To further apply such a single-cell recording approach to small brain areas in naturally behaving animals in large spaces or during social interaction, we developed a compact wireless recording system with a motorized microdrive. Wireless control of electrode placement facilitates the exploration of single neuronal activity without affecting animal behaviors. Because the system is equipped with a newly developed data-encoding program, the recorded data are readily compressed almost to theoretical limits and securely transmitted to a host computer. Brain activity can thereby be stably monitored in real time and further analyzed using online or offline spike sorting. Our wireless recording approach using a precision motorized microdrive will become a powerful tool for studying brain mechanisms underlying natural or social behaviors.

DOI： 10.1038/srep07853

Web of Science

Energy Reduction by Built-in Body Biasing with Single Supply Voltage Operation Reviewed

Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera

PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015) 181 - 185 2015

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

Energy-efficiency has become the driving force of today's LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.

DOI： 10.1109/ISQED.2015.7085421

Web of Science

PLL の物理レイアウト自動生成を目指した設計手法 Reviewed

釡江典裕, 土谷亮, 石原亨, 小野寺秀俊

情報処理学会DA シンポジウム 2014.8

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure Reviewed

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS E97C ( 4 ) 325 - 331 2014.4

Language：English Publishing type：Research paper (scientific journal) Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a radiation-hardened phase-locked loop (RH-PLL) with a switchable dual modular redundancy (DMR) structure. After radiation strikes, unhardened PLLs suffer clock perturbations. Conventional RH-PLLs have been proposed to reduce recovery time after perturbation. However, this recovery still requires tens of clock cycles. Our proposal involves 'detecting' and 'switching', rather than 'recovering' from clock perturbation. Detection speed is crucial for robust perturbation-immunity. We identify types of clock perturbation and then propose a set of detectors to detect each type. With this method, the detectors guarantee high-speed detection that leads to perturbation-immune switching from a radiated clock to an undistorted clock. The proposed RH-PLL was fabricated and then verified with a radiation test on real silicon.

DOI： 10.1587/transele.E97.C.325

Web of Science

Analysis of radiation-induced clock-perturbation in phase-locked Loop Reviewed

S.N. Kim, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 3 ) 768 - 776 2014.3

A body bias generator with low supply voltage for within-die variability compensation Reviewed

N. Kamae, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A ( 3 ) 734 - 740 2014.3

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation Reviewed

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 3 ) 734 - 740 2014.3

Language：English Publishing type：Research paper (scientific journal) Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

A body bias generator (BBG) for fine-grained body biasing (FGBB) is proposed. The FGBB is effective to reduce variability and Power consumption in a system-on-chip (SoC). Since FGBB needs a number of BBGs, the BBG is preferred to be implemented in cell-based design procedure. In the cell-based design, it is inefficient to provide an extra supply voltage for BBGs. We invented a BBG with switched capacitor configuration and it enables BBG to operate with wide range of the supply voltage from 0.6 V to 1.2 V. We fabricated the BBG in a 65 nm CMOS process to control 0.1 mm(2) of core circuit with the area overhead of 1.4% for the BBG.

DOI： 10.1587/transfun.E97.A.734

Web of Science

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop Reviewed

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A ( 3 ) 768 - 776 2014.3

Language：English Publishing type：Research paper (scientific journal) Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper presents an analysis of radiation-induced clock-perturbation in phase-locked loop (PLL). Due to a trade-off between cost, performance, and reliability, radiation hardened PLL design need robust strategy. Thus, evaluation of radiation vulnerability is important to choose the robust strategy. The conventional evaluation-method is however based on brute-force analysis - SPICE simulation and experiment. The presented analysis result eliminates the brute-force analysis in evaluation of the radiation vulnerability. A set of equations enables to predict the radiation-induced clock-perturbation at the every sub-circuits. From a demonstration, the most vulnerable nodes have been found, which are validated using a PLL fabricated with 0.18 mu m CMOS process.

DOI： 10.1587/transfun.E97.A.768

Web of Science

Radiation-hardened PLL with a switchable dual modular redundancy structure Reviewed

S.N. Kim, A. Tsuchiya, H. Onodera

IEICE Transactions on Electronics E97-C ( 4 ) 325 - 331 2014.1

25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS Reviewed

Tomoki Tanaka, Keiji Kishine, Hiromi Inaba, Akira Tsuchiya

2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 94 - 95 2014

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

A 25-Gb/s inductorless output buffer circuit with a pre-emphasis is proposed. We designed the circuit parameters according to the frequency characteristics of the emphasized signal. To confirm the advantages of the emphasis circuit, we fabricated an output buffer IC in a 65-nm CMOS process. The proposed circuit has a control voltage to adjust the emphasis amplitude according to the load outside the chip. Measurement results showed that the jitters were 40% lower with the emphasis circuit than without, indicating that our proposed configuration can be applied to the design of output buffer circuits for higher operation speed.

DOI： 10.1109/ISOCC.2014.7087578

Web of Science

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops Reviewed

Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 2704 - 2707 2014

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

A 12.5-Gb/s burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops which operate complementarily. The same type of circuit configurations are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a 12.5-Gb/s-BCDR IC with the 65-nm-MOSFET process. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gis. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW, respectively.

DOI： 10.1109/ISCAS.2014.6865731

Web of Science

A Body Bias Generator with Wide Supply-Range down to Threshold Voltage for Within-Die Variability Compensation Reviewed

Norihiro Kamae, A. K. M. Mahfuzul Islam, Akira Tsuchiya, Hidetoshi Onodera

2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) 53 - 56 2014

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. While FGBB is effective in reducing variability and power consumption, a number of BBGs are required on a die and therefore simplified design of BBGs is necessary. This paper proposes a cell-based design of a BBG that generates forward and reverse body bias voltages only from a core supply voltage ranging from the near threshold of 500mV to the nominal voltage of 1.2V. This wide operating range is achieved by a low voltage error amplifier with a V-th biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm low power CMOS process to control 0.22mm(2) of core circuit with the area overhead of 2.3% for the BBG.

DOI： 10.1109/ASSCC.2014.7008858

Web of Science

\Analysis of Radiation-Induced Timing Vulnerability on Phase- locked Loops Reviewed

S.N. Kim, A. Tsuchiya, H. Onodera

情報処理学会DA シンポジウム 2013.8

A 25-Gb/s LD Driver with Area-Effective Inductor in a 0.18-mu m CMOS Reviewed

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 105 - 106 2013

Language：English Publishing type：Research paper (international conference proceedings) Publisher：IEEE

This paper presents high-speed and area-efficient laser-diode driver with interwoven inductor in a 0.18-mu m CMOS. We interweave ten peaking inductors for area-effective implementation as well as performance enhancement. Interwoven inductor can not only achieve area-efficiency but also tune frequency characteristic. Mutual inductances of interwoven inductor enhance bandwidth and suppress group delay dispersion. The test chip area is 0.32 mm(2) and the maximum operating speed is 25 Gb/s.

DOI： 10.1109/ASPDAC.2013.6509578

Web of Science

Perturbation-immune radiation-hardened PLL with a switchable DMR structure Reviewed

Sin Nyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium, IOLTS 2013 128 - 132 2013

Language：English Publishing type：Research paper (international conference proceedings)

This paper proposes a perturbation-immune radiation-hardened PLL with a switchable dual modular redundancy (DMR) structure. By a radiation-strike, a PLL has clock-perturbation for a while. Conventional RHPLLs are proposed to reduce recovery-time which is the time to recover from perturbation. However, recovery still needs tens of clock cycles. Our proposal is 'detecting' and 'switching' instead of 'recovering' clock-perturbation. For robust perturbation-immunity, detecting speed is important. We identify types of clock-perturbation and-then propose a set of detectors to detect each type. With this, detectors guarantee high speed in detection. © 2013 IEEE.

DOI： 10.1109/IOLTS.2013.6604063

Scopus

Impact of skin effect on loss modeling of on-chip transmission-line for terahertz integrated circuits Reviewed

Akira Tsuchiya, Hidetoshi Onodera

IMFEDK 2013 - 2013 International Meeting for Future of Electron Devices, Kansai 106 - 107 2013

Language：English Publishing type：Research paper (international conference proceedings)

This paper discusses loss of on-chip transmission-line in terahertz region. Above 100 GHz, modeling of on-chip transmission-line is an important issue. We evaluate the impact of eddy current and anomalous skin effect by a field solver. Simulation results show that eddy current in dummy fills has higher impact of 10% on transmission-line loss. Anomalous skin effect is not negligible, but its impact is about 5% at 100 GHz. © 2013 IEEE.

DOI： 10.1109/IMFEDK.2013.6602261

Scopus

Advanced RF and analog integrated circuits for fourth generation wireless communications and beyond Reviewed

Ramesh Pokharel, Leonid Belostotski, Akira Tsuchiya, Ahmed Allam, Mohammad S. Hashmi

International Journal of Microwave Science and Technology 2013

A slow-wave transmission line with thin pillars for millimeter-wave CMOS Reviewed

Taro Amagai, Akira Tsuchiya, Shinsuke Nakano, Masafumi Nogawa, Hiroshi Koizumi, Hidetoshi Onodera

2013 17th IEEE Workshop on Signal and Power Integrity, SPI 2013 2013

Language：English Publishing type：Research paper (international conference proceedings)

This paper presents a slow-wave transmission line with thin pillars on strips shield. Slow-wave transmission lines are mostly used as stub filters. The proposed structure with pillars has higher capacitance and inductance per unit length of the line. Thus, high phase constant and quality factor can be achieved. We compare simulation results between the proposed structure and conventional lines for millimeter-wave CMOS. The proposed line gives higher phase constant of 3.1 rad/mm and high quality factor of 21.6 at 60 GHz. © 2013 IEEE.

DOI： 10.1109/SaPIW.2013.6558341

Scopus

Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation Reviewed International journal

A. K. M. Mahfuzul Islam, A. Tsuchiya, K. Kobayashi, H. Onodera

IEEE Transactions on Semiconductor Manufacturing 25 ( 4 ) 571 - 580 2012.11

A Body Bias Generator Compatible with Cell-based Design Flow for Within-die Variability Compensation Reviewed

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEEE Asian Solid-State Circuits Conference(A-SSCC) 2012, pp. 389-392, Nov 2012. 2012.11

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Papers - TSUCHIYA Akira