研究者詳細 - 土谷　亮

論文 - 土谷　亮

分割表示174 件中 21 - 40 件目／全件表示 >>

A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver 査読国際誌

Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 644 - 647 2022年2月

Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems 査読国際誌

Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine

International Conference on Electronics, Information, and Communication 616 - 619 2022年2月

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier 査読国際誌

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, and Makoto Nakamura

International Conference on Electronics, Information, and Communication 640 - 643 2022年2月

Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS 査読国際誌

Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

The 27th Asia and South Pacific Design Automation Conference 96 - 97 2022年1月

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks 査読国際誌

T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura

28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) 1 - 6 2021年11月

Dynamic Memory Access Control for Accelerating FPGA-based Image Processing 査読国際誌

Kenta Nishiguchi, Toshiyuki Inoue, Rei Yamazaki, Kazunori Ogohara, Akira Tsuchiya, Keiji Kishine

Journal of Semiconductor Technology and Science 21 ( 1 ) 29 - 38 2021年2月

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS 査読

Ichii Y., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

This paper proposes a 5-Gb/s four-level pulse amplitude modulation (PAM4) transmitter using compensation circuit in data transmission systems. In PAM4 systems, the signal amplitude requires smaller rising and falling times. To achieve this, we adopted an analog feed forward equalizing (FFE) for the compensation in PAM4 transmitter. To confirm the advantage of the proposed technique, we fabricated a 5-Gb/s PAM4 transmitter IC in an 180-nm CMOS process for this work. The measured rising and falling times were 18% and 13% smaller than those without FFE, respectively.

DOI： 10.1109/ICEIC51217.2021.9369819

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85102971150&origin=inward

Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA 査読

Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

2021 International Conference on Electronics, Information, and Communication, ICEIC 2021 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：2021 International Conference on Electronics, Information, and Communication, ICEIC 2021

Regression and classification are necessary for biometric systems and carried out using machine learning. A method for regression and classification is long short-term memory (LSTM). We proposed and implemented algorithms for low-energy LSTM for the regression of microwave-sensor signals into a small-scale FPGA. We found that our FPGA-based parallel (including unrolled)-pipelined algorithm decreased the computation time by 95% compared with the FPGA-based sequential algorithm. In addition, the amount of energy consumption with the proposed algorithm was reduced by 92% and 91% compared with that with a high-end GPU and CPU, respectively.

DOI： 10.1109/ICEIC51217.2021.9369806

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85102974307&origin=inward

Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers 査読国際誌

Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

Asia-South Pacific Design Automation Conference 15 - 16 2021年1月

A Method for Accelerating the Inference Process of FPGA-based LSTM for Biometric Systems 査読

Yoshimura U., Inoue T., Tsuchiya A., Kishine K.

IEIE Transactions on Smart Processing and Computing 10 ( 5 ) 416 - 423 2021年1月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEIE Transactions on Smart Processing and Computing

Biometric systems require the regression and classification of biological sensing data, which are both carried out using machine learning. Long short-term memory (LSTM) is one of the most common methods used for regression and classification. We have developed and implemented a low-energy LSTM algorithm for the regression of microwave sensor signals in a small-scale FPGA. Experimental results show that the FPGA-based parallel-pipelined unrolled algorithm can reduce the computation time by 95% compared to an FPGA-based sequential algorithm. In addition, we found that the power consumption can be reduced by 92% and 91% compared to that obtained with a high-end GPU and CPU, respectively.

DOI： 10.5573/IEIESPC.2021.10.5.416

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85119718234&origin=inward

Processing Time Reduction for JPEG Compression Using Pixel Array Conversion 査読国際誌

Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

17th International SoC Design Conference 2020年10月

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS 査読国際誌

Akira TSUCHIYA, Akitaka HIRATSUKA, Kenji TANAKA, Hiroyuki FUKUYAMA, Naoki MIURA, Hideyuki NOSAKA, Hidetoshi ONODERA

IEiCE Transactions on Electronics E103-C ( 10 ) 489 - 496 2020年10月

Design of On-Chip Multi-layered Inductor for Area-Efficient Inductive Peaking 招待査読国際誌

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine

2020 IEEE International Symposium on Radio-Frequency Integration Technology 12 - 14 2020年9月

Design method for active-shunt-feedback type inductorless low-noise amplifiers in 65-nm CMOS 査読

Inoue T., Tsuchiya A., Kishine K.

Journal of Semiconductor Technology and Science 20 ( 2 ) 177 - 186 2020年4月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Journal of Semiconductor Technology and Science 参加形態：共同（副担当）

© 2020, Institute of Electronics Engineers of Korea. All rights reserved. We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, band-width, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-mm CMOS type.

DOI： 10.5573/JSTS.2020.20.2.177

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85084141823&origin=inward

Capacitive Sensor for Contact Angle Estimation of Droplet on Microfluidic Chip 査読国際誌

Akira Tsuchiya, Toshiyuki Inoue and Keiji Kishine

2019 Asia-Pacific Microwave Conference 2019年12月

Frequency Discriminator Using a Simple AD Converter for Interface Systems 査読国際誌

Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

16th International SoC Design Conference 2019年10月

Optimization Technique of Memory Traffic for FPGA-Based Image Processing System 査読国際誌

Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara and Keiji Kishine

16th International SoC Design Conference 2019年10月

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS 査読国際誌

Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya and Keiji Kishine

16th International SoC Design Conference 2019年10月

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS 査読国際誌

Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

32nd International System-on-Chip Conference 2019年9月

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier 査読国際誌

Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine

32nd IEEE International System-on-Chip Conference 2019年9月

　前のページ - 次のページ　

<土谷 亮>

論文 - 土谷 亮

<土谷　亮>

論文 - 土谷　亮