研究者詳細 - 土谷　亮

論文 - 土谷　亮

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Statistical gate delay model for multiple input switching 査読

T. Fukuoka, A. Tsuchiya, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E92-A ( 12 ) 3070 - 3078 2009年12月

Statistical Gate Delay Model for Multiple Input Switching 査読

Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A ( 12 ) 3070 - 3078 2009年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

In this paper, we propose a calculation method of gate delay for SSTA (Statistical Static Timing Analysis) considering MIS (Multiple Input Switching). In SSTA, statistical maximum/minimum operation is necessary to calculate the latest/fastest arrival time of multiple input gate. Most SSTA approaches calculate the distribution in the latest/fastest arrival time under SIS (Single Input Switching assumption), resulting in ignoring the effect of MIS on the gate delay and the Output transition time. MIS occurs when multiple inputs of a gate switch nearly simultaneously. Thus, ignoring MIS causes error in the statistical maximum/minimum operation in SSTA. We propose a statistical gate delay model considering MIS. We verify the proposed method by SPICE based Monte Carlo simulations. Experimental results show that the neglect of MIS effect leads to 80% error in worst case. The error of the proposed method is less than 20%.

DOI： 10.1587/transfun.E92.A.3070

Web of Science

チップ内ばらつきが順序セルの動作特性に与える影響査読

砂川洋輝, 土谷亮, 小林和淑, 小野寺秀俊

情報処理学会DA シンポジウム 2009年8月

Effect of Regularity-Enhanced Layout on Printability and Circuit Performance of Standard Cells 査読

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2 195 - 200 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-off among manufacturability, cost, and performance for each process technology. This paper discusses the efiect of layout regularity on printability and circuit performance in 90 45nm processes by lithography simulation and real chip measurement. It is shown that we can focus more on circuit performance with less on layout regularity in a 90nm process while adequate amount of regularity is imperative for ensuring proper amount of lithographic process windows in a 45nm process. We demonstrate the quantitative evaluation of the trade-off between printability and circuit performance of regularity-enhanced standard cells.

DOI： 10.1109/ISQED.2009.4810293

Web of Science

On-Chip Metamaterial Transmission-Line Based on Stacked Split-Ring Resonator for Millimeter-Wave LSIs 査読

Akira Tsuchiya, Hidetoshi Onodera

APMC: 2009 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 1458 - 1461 2009年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a method to realize on-chip metamaterial transmission-line. Since the resonant frequency of split-ring resonator (SRR) depends on the size strongly, it is difficult to realize metamaterial transmission-line in integrated circuits. If we implement a conventional SRR to on-chip transmission-line, the resonant frequency is around 200GHz. We propose a stacked SRR using on-chip multi-layer interconnect. The stacked SRR is evaluated by a field-solver and the experimental results verify that the stacked SRR can realize the resonant frequency below 60GHz.

DOI： 10.1109/APMC.2009.5384480

Web of Science

High performance on-chip differential signaling using passive compensation for global communication 査読

L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E.S. Kuh, C.-K. Cheng

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 385 - 390 2009年

Effect of underlayer dummy fills on on-chip transmission line 査読

A. Tsuchiya, H. Onodera

2009 IEEE Workshop on Signal Propagation on Interconnects, SPI \\'09 2009年

Analytical eye-diagram model for on-chip distortionless transmission lines and its application to design space exploration 査読

M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A ( 12 ) 3474 - 3480 2008年12月

Patterned floating dummy fill for on-chip spiral inductor considering the effect of dummy fill 査読国際誌

A. Tsuchiya, H. Onodera

IEEE Transactions on Microwave Theory and Techniques 56 ( 12 ) 3217 - 3222 2008年12月

Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration 査読

Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A ( 12 ) 3474 - 3480 2008年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.

DOI： 10.1093/ietfec/e91-a.12.3474

Web of Science

Patterned Floating Dummy Fill for On-Chip Spiral Inductor Considering the Effect of Dummy Fill 査読

Akira Tsuchiya, Hidetoshi Onodera

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 56 ( 12 ) 3217 - 3222 2008年12月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper discusses the effect of dummy fills on the performance of spiral inductors. In Si-CMOS processes that use copper wire, metal dummy fills are required to prevent thickness fluctuation in the chemical mechanical polishing stage. Dummy fills have been thought to affect the wire capacitance; however, in high frequency, dummy fills also affect the wire resistance and the wire inductance due to the eddy current in dummy fills. This work evaluates the effect of the dummy fills by three-dimensional field solver and proposes a structure to suppress the effect of dummy fills. Experimental results show that the proposed method can decrease the effect of dummy fills on the Q-factor by 83% compared with the conventional dummy fill insertion.

DOI： 10.1109/TMTT.2008.2007362

Web of Science

Accurate estimation of the worst-case delay in statistical static timing analysis 査読

H. Terada, T. Fukuoka, A. Tsuchiya, H. Onodera

IPSJ Transactions on System LSI Design Methodology 1 116 - 125 2008年8月

Accurate estimation of the worst-case delay in statistical static timing analysis 査読

Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera

IPSJ Transactions on System LSI Design Methodology 1 116 - 125 2008年8月

記述言語：英語掲載種別：研究論文（学術雑誌）

In this paper, we propose an approximation method for the statistical MAX operation such that it results in a normal distribution good for the worst-case delay analysis. The important operation in SSTA is SUM and MAX of distributions. In general, the delay variation is modeled as normal distribution. The result of SUM operation of two normal distributions is also normal distribution. On the other hand, the result of MAX operation is not normal distribution. Thus approximation to normal distribution is commonly used. We also explain that the proposed MAX operation at each gate also contributes to the accurate estimation in the worst-case delay analysis of the whole circuit. Experimental results show that the proposed method leads to a good approximation for a normal distribution resulted from MAX operation of normal distributions with and without correlation, and the approximation improves the accuracy of the worst-case delay analysis. In a circuit example, the errors of worst-case delay computed by the previous method are about 20%, and the errors computed by the proposed method are under 5%. © 2008 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.1.116

Scopus

リングオシレータアレイによるゲート遅延ばらつきの評価とモデル化査読

寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2008 ( 7 ) 199 - 204 2008年8月

レイアウト規則性が回路性能とばらつきに及ぼす影響の評価査読

砂川洋輝, 寺田晴彦, 土谷亮, 小林和淑, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2008 ( 7 ) 67 - 72 2008年8月

Dummy fill insertion considering the effect on high-frequency characteristics of spiral inductors 査読

A. Tsuchiya, H. Onodera

IEEE MTT-S International Microwave Symposium Digest 787 - 790 2008年

On-chip high performance signaling using passive compensation 査読

Z. Yulei, Z. Ling, A. Tsuchiya, M. Hashimoto, C.-K. Cheng

26th IEEE International Conference on Computer Design 2008, ICCD 182 - 187 2008年

Statistical gate delay model for multiple input switching 査読

T. Fukuoka, A. Tsuchiya, H. Onodera

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 286 - 291 2008年

同時スイッチングを考慮した統計的遅延解析査読

福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2007 ( 7 ) 13 - 18 2007年8月

統計的遅延解析における遅延分布間の最大値計算手法査読

寺田晴彦, 福岡孝之, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2007 ( 7 ) 7 - 12 2007年8月

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