研究者詳細 - 土谷　亮

論文 - 土谷　亮

分割表示174 件中 81 - 100 件目／全件表示 >>

Variation-Sensitive Monitor Circuits for Estimation of Global Process Parameter Variation 査読

Islam A. K. M. Mahfuzul, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 25 ( 4 ) 571 - 580 2012年11月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation.

DOI： 10.1109/TSM.2012.2198677

Web of Science

Dual-PLL based on Temporal Redundancy for Radiation-Hardening 査読

SinNyoung KIM, Akira TSUCHIYA, Hidetoshi ONODERA

Proceedings of 10th International Workshop on Radiation Effects on Semiconductor Devices for Space Applications 2012年10月

Modeling of Single-Event Failures in Dividerand PFD of PLLs based on Jitter Analysis 査読

SinNyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

13th European Conference on Radiation and Its Effects on Components and Systems (RADECS), Sep 2012. 2012年9月

チップ内基板バイアス生成回路のモジュール化設計査読

釡江典裕, 土谷亮, 小野寺秀俊

情報処理学会DAシンポジウム2012論文集, pp. 55-60, Aug 2012. 2012年8月

Area-effective inductive peaking with interwoven inductor for high-speed laser-diode driver for optical communication system 査読

T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95-A ( 2 ) 479 - 486 2012年2月

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System 査読

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A ( 2 ) 479 - 486 2012年2月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 mu m CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

DOI： 10.1587/transfun.E95.A.479

Web of Science

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18μm CMOS 査読

T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 561 - 562 2012年

Impact of radiation loss in on-chip transmission-line for terahertz applications 査読

Akira Tsuchiya, Hidetoshi Onodera

2012 IEEE 16th Workshop on Signal and Power Integrity, SPI 2012 - Proceedings 125 - 128 2012年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper discusses radiation loss of on-chip transmission-line. Since terahertz applications of integrated circuits are emerging, precise modeling in terahertz region is needed. We evaluate conductor loss, dielectric loss and radiation loss of on-chip transmission-line by a full-wave field solver. Simulation results show that design focusing conductor loss may cause large radiation loss in terahertz region. Quantitative evaluation of the impact of radiation loss is demonstrated. Also we show that thick signal wire and differential line is effective to reduce the loss. © 2012 IEEE.

DOI： 10.1109/SaPIW.2012.6222926

Scopus

A 10.3Gbps transimpedance amplifier with mutually coupled inductors in 0.18-μm CMOS 査読

S. Miyawaki, M. Nakamura, A. Tsuchiya, K. Kishine, H. Onodera

2011 International SoC Design Conference, ISOCC 2011 223 - 226 2011年

Gradient Resistivity Method for Numerical Evaluation of Anomalous Skin Effect 査読

Akira Tsuchiya, Hidetoshi Onodera

2011 15TH IEEE WORKSHOP ON SIGNAL PROPAGATION ON INTERCONNECTS (SPI) 139 - 142 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper discusses a method to evaluate anomalous skin effect. Anomalous skin effect (ASE) is a phenomenon which appears when the skin depth becomes comparable to the mean free path of electrons. In anomalous region, the effective resistivity depends on skin depth. Thus it is difficult to evaluate by field-solvers. The proposed method realizes field simulation considering ASE by gradient resistivity. Simulation result shows that the resistance increase more rapid than classical skin effect above 100GHz. The effect on the resistance is 5% at 100GHz and 10% at 300GHz.

DOI： 10.1109/SPI.2011.5898859

Web of Science

An area effective forward/reverse body bias generator for within-die variability compensation 査読

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011 217 - 220 2011年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

To compensate the die-to-die and location correlated variation, we propose to split digital circuit to sub-mm-scale area controlling each area with an on-chip forward/reverse body bias generator (BBG). The proposed BBG is configured as a feedforward control system to achieve small area. The BBG is realized by combining a low output resistance DAC and a charge pump type level shifter. The BBG design is implemented with 1.2V thin gate oxide MOSFET in a 65nm CMOS technology. The simulation and measurement results show that the variation is compensated with an area overhead as small as 2%. © 2011 IEEE.

DOI： 10.1109/ASSCC.2011.6123641

Scopus

Variation-sensitive monitor circuits for estimation of die-to-die process variation 査読

I.A.K.M. Mahfuzul, A. Tsuchiya, K. Kobayashi, H. Onodera

IEEE International Conference on Microelectronic Test Structures 153 - 157 2011年

レイアウト制約が性能と製造性に与える影響査読

北島和彦, 砂川洋輝, 土谷亮, 小野寺秀俊, 小野寺秀俊

情報処理学会DAシンポジウム論文集 2010 ( 7 ) 221 - 226 2010年8月

Effect of regularity-enhanced layout on variability and circuit performance of standard cells 査読

H. Sunagawa, H. Terada, A. Tsuchiya, K. Kobayashi, H. Onodera

IPSJ Transactions on System LSI Design Methodology 3 130 - 139 2010年2月

A 16Gbps Laser-Diode Driver with Interwoven Peaking Inductors in 0.18-mu m CMOS 査読

Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera

IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

A laser-diode (LD) driver with interwoven mutually-coupled peaking inductors for high-speed optical networks is presented. Six and four inductors are interwoven into two sets of inductors for area-effective implementation as well as performance enhancement. The proposed circuit is fabricated in CMOS 0.18-mu m process. The circuit area is 0.34mm(2) and the maximum operating speed is 16Gbps. Compared to a conventional LD driver in 0.18-mu m CMOS, the proposed circuit achieves 1.6 times faster operation, 26% smaller area with 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current.

DOI： 10.1109/CICC.2010.5617416

Web of Science

Measurement of on-chip transmission-line with stacked split-ring resonators 査読

Akira Tsuchiya, Hidetoshi Onodera

2010 IEEE 14th Workshop on Signal Propagation on Interconnects, SPI 2010 - Proceedings 137 - 140 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

This paper reports measurement results of on-chip transmission-line with split-ring resonators. Split-ring resonator (SRR) has attracted attention as an implementation of metamaterial (left-handed material). However when simple SRR is implemented in LSIs, the resonance frequency becomes around 200GHz and it is too high to employ on on-chip circuits. We designed a stacked SRR to lower the resonant frequency in a 0.18//m CMOS. Measurement results show that the stacked SRRs can realize the resonance frequency below 50GHz. Also measurement results show a guideline of area effective implementation of on-chip SRR. © 2010 IEEE.

DOI： 10.1109/SPI.2010.5483544

Scopus

Effect of regularity-enhanced layout on variability and circuit performance of standard cells 査読

Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

IPSJ Transactions on System LSI Design Methodology 3 130 - 139 2010年

記述言語：英語掲載種別：研究論文（学術雑誌）

As the minimum feature size shrinks down far below sub-wavelength, Design for Manufacturability or layout regularity plays an important role for maintaining pattern fidelity in photolithography. However, it also incurs overheads in circuit performances due to parasitic capacitance. In this paper, we examine the effect of layout regularity on printability and circuit performance by lithography simulation and transistor-level simulation. It is shown that regularity-enhanced cells provide better Critical Dimension (CD) stability under defocus and lead to delay increase. Then we evaluate the effect of layout regularity by a real chip measurement in 90 nm, 65 nm and 45 nm processes. For example, in a 65 nm process, inverter Ring Oscillators (ROs) that have the smallest poly pitch with dummy-poly insertion exhibits 19% reduction of WID and D2D variation with delay overhead of 2.5%, compared to the ROs without dummy-poly insertion. However, we have observed that the effect of layout regularity varies depending on fabrication processes and circuit structures. It is therefore important to obtain the best trade-off among performance overhead and variability reduction for each process technology. © 2010 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.3.130

Scopus

A design procedure of predictive RF MOSFET model for compatibility with ITRS 査読

Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera

Proceedings - IEEE International SOC Conference, SOCC 2010 396 - 399 2010年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

A design procedure for generating predictive MOS-FET models is proposed. Due to evolving nature of future prediction, predictive models based on a certain prediction soon become absolute. We have therefore developed a design procedure for maintaining compatibility with most up-to-date prediction such as ITRS. The design procedure can generate predictive RF models for the first time. Details of the design procedure for BSIM4 as a core model are explained, with an application to LNA design example. © 2010 IEEE.

DOI： 10.1109/SOCC.2010.5784704

Scopus

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-μm CMOS 査読

T. Kuboki, Y. Ohtomo, A. Tsuchiya, K. Kishine, H. Onodera

Proceedings of the Custom Integrated Circuits Conference 2010年

Process-sensitive Monitor Circuits for Estimation of Die-to-Die Process Variability 査読

A.K.M Mahfuzul Islam, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera

Tau Workshop 2010, Mar 2010. 2010年

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