研究者詳細 - 土谷　亮

論文 - 土谷　亮

分割表示174 件中 141 - 160 件目／全件表示 >>

Analytical estimation of interconnect loss due to dummy fills 査読

A. Tsuchiya, H. Onodera

Electrical Performance of Electronic Packaging, EPEP 149 - 152 2006年

Low-Power Design of CML Drivers for On-Chip Transmission-Lines 査読

Akira Tsuchiya, Takeshi Kuboki, Hidetoshi Onodera

SASIMI2006,pp. 177-182 2006年

Interconnect RL extraction at a single representative frequency 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 515 - 520 2006年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper proposes a method to determine a single frequency for interconnect RL extraction. Resistance and inductance of interconnects depend on frequency, and hence the extraction frequency strongly affects the modeling accuracy of interconnects. The proposed method determines an extraction frequency based on the transfer characteristic of interconnects. By choosing the frequency where the transfer characteristic becomes maximum, the extracted RL values achieve the accurate modeling of the waveform. We experimentally verify that the proposed method provides accurate transition waveforms over various interconnect topologies.

Web of Science

Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction 査読

T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto

International Workshop on Compact Modeling, pp. 51-56, 2006. 2006年

A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection

Akira Tsuchiya

2005年11月

A Study on Modeling and Design Methodology for High-Performance On-Chip Interconnection 査読

Kyoto University 2005年11月

CMLを用いたオンチップ長距離高速信号伝送技術の開発

土谷亮, 新名亮規, 橋本昌宜, 小野寺秀俊

第9回システムLSIワークショップ, pp.275--278, Nov 2005. 2005年11月

Performance Limitation of On-chip Global Interconnects for High-speed Signaling 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A ( 4 ) 885 - 891 2005年4月

Design guideline for resistive termination of on-chip high-speed interconnects 査読

A. Tsuchiya, M. Hashimoto, H. Onodera

Proceedings of the Custom Integrated Circuits Conference 2005 608 - 611 2005年

Effects of Orthogonal Power/Ground Wires on On-chip Interconnect Characteristics 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

2005 International Meeting for Future Electron Devices, Kansai, pp.33-34, Apr 2005. 2005年

Performance prediction of on-chip high-throughput global signaling 査読

Masanori Hashimoto, Akira Tsuchiya, Akinori Shinmyo, Hidetoshi Onodera

IEEE Topical Meeting on Electrical Performance of Electronic Packaging 2005 79 - 82 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）

On-chip global signaling whose performance improves with technology advance is eagerly demanded. This work focuses on wave pipelining on on-chip transmission lines, which is one of probable solutions, and predicts the trend of signaling performance in the future. Experiments reveal that transmission capacity per channel will improve till at least 35nm technology in 10mm-long or below signaling. We also demonstrate that current-mode differential signaling is robust against power supply noise, but power delivery with non-zero impedance degrades the performance. © 2005 IEEE.

DOI： 10.1109/EPEP.2005.1563706

Scopus

配線の伝達特性に基づく抽出周波数決定手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

DAシンポジウム 2005, pp.169-174, Aug 2005. 2005年

オンチップ高速信号伝送における終端抵抗決定手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

第18回回路とシステム軽井沢ワークショップ, pp.425-430, Apr 2005. 2005年

Substrate loss of on-chip transmission-lines with power/ground wires in lower layer 査読

A Tsuchiya, M Hashimoto, H Onodera

SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS 2005 201 - 202 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper discusses shielding effect of power/ground wires in lower layer. A conducting substrate affects characteristics of on-chip transmission line. However in many cases on actual chips, there are P/G wires between the signal wire and the substrate that may shield the substrate coupling. We show measurement and simulation results of on-chip transmission-lines with narrow yet many power/ground wires in a lower layer. Experimental results show that narrow power/ground wires in a lower layer in parallel to the signal wire, which are common in LSI power distribution network, shield substrate coupling and suppress substrate loss. On the other hand, orthogonal power/ground wires in a lower layer hardly mitigate substrate coupling.

DOI： 10.1109/SPI.2005.1500944

Web of Science

Return path selection for loop RL extraction 査読

Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 2 1078 - 1081 2005年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper propose a systematic method to select power/ground wires that should be considered in interconnect R-L extraction. The return current distribution affects loop characteristic of interconnects. To extract exact RL value, all of return paths have to be considered. However it is impossible because there are huge number of P/G wires in LSIs. As more wires are considered, the extraction accuracy improves but the extraction cost increases undesirably. The proposed method focuses the energy dissipated at P/G wires and utilizes it for screening return paths. Experimental results reveal that our method enables accurate and computationally efficient RL extraction with considering return current distribution.

Web of Science

On-chip global signaling by wave pipelining 査読

M Hashimoto, A Tsuchiya, H Onodera

ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING 311 - 314 2004年

記述言語：英語掲載種別：研究論文（国際会議プロシーディングス）出版者・発行元：IEEE

This paper discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.

Web of Science

Performance limitation of on-chip global interconnects for high-speed signaling 査読

A. Tsuchiya, Y. Gotoh, M. Hashimoto, H. Onodera

Proceedings of the Custom Integrated Circuits Conference 489 - 492 2004年

Performance Prediction of On-chip Global Signaling 査読

M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera

3rd Electrical Design of Avdanced Packaging and Systems Workshop, pp.87-100, Nov 2004. 2004年

配線RL抽出におけるリターンパス選択手法査読

土谷亮, 橋本昌宜, 小野寺秀俊

DAシンポジウム 2004, pp.175-180, Jul 2004. 2004年

オンチップ伝送線路のリターン電流分布が信号波形に与える影響 — 平衡・不平衡伝送の比較 — 査読

土谷亮, 橋本昌宜, 小野寺秀俊

第17回回路とシステム軽井沢ワークショップ, pp.567-572, Apr 2004. 2004年

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