研究者詳細 - 土谷　亮

論文 - 土谷　亮

分割表示174 件中 41 - 60 件目／全件表示 >>

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity 査読

Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA

IEICE TRANSACTIONS on Electronics E102-C ( 7 ) 573 - 579 2019年7月

FPGA-based binary labeling signal transmission system 査読

Inoue T., Nomura K., Noguchi R., Koda N., Tsuchiya A., Kishine K.

Journal of Semiconductor Technology and Science 19 ( 3 ) 276 - 286 2019年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：Journal of Semiconductor Technology and Science

© 2019, Institute of Electronics Engineers of Korea. All rights reserved. We implemented and evaluated our newly developed binary labeling signal transmission system using field-programmable gate arrays. In this system, the state of “0” or “1” of labeling signals is related to modulation or non-modulation of frame signals, and the labeling signals can be multiplexed to frame signals and transmitted without changing the configuration of the original frame signal. We designed a modulation-system protocol for implementing the above system and propose a digital smoothing technique for stabilizing a phase-locked loop circuit. We verified that our digital smoothing technique prevents bit error of the modulated frame signals in the implemented transmitter. The labeling signal multiplexed to the frame signals is demodulated without bit error in the implemented transceiver.

DOI： 10.5573/JSTS.2019.19.3.276

Scopus

その他リンク： https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85070491085&origin=inward

A 25-Gb/s Low-Power Clock and Data Recovery with an ActiveStabilizing CML-CMOS Conversion 査読国際誌

Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine

The 25th IEEE International Conference on Electronics Circuits and Systems 2018年12月

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-less Bandwidth Compensation 査読国際誌

Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera

IEEE Asian Solid-State Circuits Conference 69 - 72 2018年11月

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback 査読国際誌

Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, and Hidetoshi Onodera

The 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2018) 2018年8月

Impact of On-Chip Multi-Layered Inductor on Signal and Power Integrity of Underlying Power-Ground Net 査読国際誌

Akira TSUCHIYA, Akitaka HIRATSUKA, Toshiyuki INOUE, Keiji KISHINE, Hidetoshi ONODERA

IEEE Workshop on Signal and Power Integrity 1 - 4 2018年5月

A 25-Gb/s 13 mW Clock and Data Recovery Using C2MOS D-Flip-Flop in 65-nm CMOS 査読国際誌

Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka

International Symposia on VLSI Design, Automation and Test 2018年4月

Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS 査読国際誌

Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura

International SoC Design Conference 2017年11月

FPGA-Based Transceiver Circuit for Labeling Signal Transmission System 査読国際誌

Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

International SoC Design Conference 2017年11月

Compact Implementation IIR Filter in FPGA for Noise Reduction of Sensor Signal 査読国際誌

Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine

International SoC Design Conference 2017年11月

Power-Bandwidth Trade-Off Analysis of Multi-Stage Inverter-Type Transimpedance Amplifier for Optical Communication 査読国際誌

Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera

MWSCAS2017 2017年8月

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS 査読国際誌

T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto

IEIE Transactions on Smart Signal and Computing 5 ( 3 ) 207 - 214 2016年6月

A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS 査読

T. Tanaka, K. Kishine, A. Tsuchiya, H. Inaba, D. Omoto

IEIE Transactions on Smart Signal and Computing 5 ( 3 ) 207 - 214 2016年6月

A 32-Gb/s output buffer circuit with doubled pre-emphasis in 65-nm CMOS 査読

International Conference on Electronics, Information, and Communication 2016年1月

A 25-Gb/s 480-mW CMOS Modulator Driver Using Area-Efficient 3D Inductor Peaking 査読

IEEE Asian Solid-State Circuits Conference 2015年11月

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage 査読

N. Kamae, A. Tsuchiya, H. Onodera

IEICE Transactions on Electronics 98-C ( 6 ) 504 - 511 2015年6月

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage 査読

Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera

IEICE TRANSACTIONS ON ELECTRONICS E98C ( 6 ) 504 - 511 2015年6月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG

A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5V to 1.2V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65 nm CMOS process. Area of the AES core is 0 : 22 mm(2) and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5V to 1.2V which enables the reduction of power dissipation, for example, of 17% at 400MHz operation.

DOI： 10.1587/transele.E98.C.504

Web of Science

Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 査読

K. Kishine, H. Inaba, H. Inoue, M. Nakamura, A. Tsuchiya, H. Katsurai, H. Onodera

IEEE Transactions on Circuits and Systems I 62 ( 5 ) 1288 - 1295 2015年5月

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS 査読

Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 62 ( 5 ) 1288 - 1295 2015年5月

記述言語：英語掲載種別：研究論文（学術雑誌）出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

A multi-rate burst-mode clock and data recovery ( BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. A simple symmetric circuit topology makes the area for the GVCO smaller and leads to an easier timing design. The GVCO consists of two loops that operate complementarily. Circuit configurations of the same type are adopted for AND and OR in the loops to reduce the difficulties in the timing alignment of the signals from the loops. To confirm the validity of the proposed topology, we fabricated a BCDR IC with the 65-nm-MOSFET process. It can extract the 12.5-GHz clock signal from 12.5-Gb/s, 6.25-Gb/s, 3.125-Gb/s, 1.5625-Gb/s, and 781.25-Mb/s input data. Without a circuit for precise timing adjustment for the signals in the two loops, the IC provides instantaneous phase locking of 1 bit for burst data input of 12.5 Gb/s. The measured jitter is lower than 2 ps rms. The area and the power consumption for the core GVCO are 0.03 mm(2) and 60 mW.

DOI： 10.1109/TCSI.2015.2416812

Web of Science

A wireless neural recording system with a precision motorized microdrive for freely behaving animals 査読国際誌

T. Hasegawa, H. Fujimoto, K. Tashiro, M. Nonomura, A. Tsuchiya, D. Watanabe

Scientific Reports 5 ( 7853 ) 2015年1月

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